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mtvec vectored mode #755
mtvec vectored mode #755
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test/asm/interrupt_vectored.asm
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# load state | ||
mv x1, x12 | ||
mv x2, x13 | ||
mv x3, x14 | ||
# fibonacci step | ||
beq x3, x15, skip | ||
add x3, x2, x1 | ||
mv x1, x2 | ||
mv x2, x3 | ||
# store state | ||
mv x12, x1 | ||
mv x13, x2 | ||
mv x14, x3 | ||
j skip |
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This a common section int0_handler, it can just jump inside there to avoid code duplication.
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Two handlers use different registers, that stores global state checked in the test, only 4 middle lines are the same. I shortened it by removing the load state and store state sections
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Looks good to merge after resolving comments, thanks!
Implement vectored interrupt mode in mtvec (issue #745)