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mtvec vectored mode #755

Merged
merged 9 commits into from
Nov 26, 2024
Merged

mtvec vectored mode #755

merged 9 commits into from
Nov 26, 2024

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kalinf
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@kalinf kalinf commented Nov 19, 2024

Implement vectored interrupt mode in mtvec (issue #745)

coreblocks/backend/retirement.py Outdated Show resolved Hide resolved
coreblocks/priv/csr/csr_instances.py Outdated Show resolved Hide resolved
test/test_core.py Outdated Show resolved Hide resolved
test/asm/interrupt_vectored.asm Outdated Show resolved Hide resolved
Comment on lines 100 to 113
# load state
mv x1, x12
mv x2, x13
mv x3, x14
# fibonacci step
beq x3, x15, skip
add x3, x2, x1
mv x1, x2
mv x2, x3
# store state
mv x12, x1
mv x13, x2
mv x14, x3
j skip
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This a common section int0_handler, it can just jump inside there to avoid code duplication.

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Two handlers use different registers, that stores global state checked in the test, only 4 middle lines are the same. I shortened it by removing the load state and store state sections

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@piotro888 piotro888 linked an issue Nov 19, 2024 that may be closed by this pull request
@piotro888 piotro888 added the enhancement New feature or request label Nov 19, 2024
@piotro888 piotro888 added this to the Implement machine mode ISA milestone Nov 19, 2024
@kalinf kalinf requested a review from piotro888 November 24, 2024 12:46
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Looks good to merge after resolving comments, thanks!

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@tilk tilk merged commit 40c82ee into kuznia-rdzeni:master Nov 26, 2024
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github-actions bot pushed a commit that referenced this pull request Nov 26, 2024
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Implement vectored interrupt mode in mtvec
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