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Implement vectored interrupt mode in mtvec #745

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piotro888 opened this issue Nov 4, 2024 · 0 comments · Fixed by #755
Closed

Implement vectored interrupt mode in mtvec #745

piotro888 opened this issue Nov 4, 2024 · 0 comments · Fixed by #755
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@kalinf
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enhancement New feature or request good first issue Good for newcomers nice to have Could be useful, but not a top priority
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Implement machine...

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@piotro888
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Defined in 3.1.7. Machine Trap-Vector Base-Address Register

Currently only direct mode is supported, where all traps set pc to mtvec value.
Vectored mode uses different pc offsets for trap cause codes

This is an optional feature.
@piotro888 piotro888 added enhancement New feature or request nice to have Could be useful, but not a top priority labels Nov 4, 2024
@piotro888 piotro888 added this to the Implement machine mode ISA milestone Nov 4, 2024
@piotro888 piotro888 added the good first issue Good for newcomers label Nov 4, 2024
@kalinf kalinf mentioned this issue Nov 19, 2024
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@piotro888 piotro888 linked a pull request Nov 19, 2024 that will close this issue
mtvec vectored mode #755
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@tilk tilk closed this as completed in #755 Nov 26, 2024
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@kalinf kalinf

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enhancement New feature or request good first issue Good for newcomers nice to have Could be useful, but not a top priority
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Implement machine mode ISA
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mtvec vectored mode kalinf/coreblocks
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