Autumn cleaning: layouts

coreblocks/core.py

@@ -75,8 +75,8 @@ def __init__(self, *, gen_params: GenParams, wb_instr_bus: WishboneBus, wb_data_
             gen=self.gen_params,
             get_result=self.func_blocks_unifier.get_result,
             rob_mark_done=self.ROB.mark_done,
-            rs_write_val=self.func_blocks_unifier.update,
-            rf_write_val=self.RF.write,
+            rs_update=self.func_blocks_unifier.update,
+            rf_write=self.RF.write,
         )
 
         self.csr_generic = GenericCSRRegisters(self.gen_params)

coreblocks/frontend/decode.py

@@ -42,7 +42,7 @@ def elaborate(self, platform):
         with Transaction().body(m):
             raw = self.get_raw(m)
 
-            m.d.top_comb += instr_decoder.instr.eq(raw.data)
+            m.d.top_comb += instr_decoder.instr.eq(raw.instr)
 
             # Jump-branch unit requires information if the instruction was
             # decoded from a compressed instruction. To avoid adding a new signal

coreblocks/frontend/fetch.py

@@ -82,7 +82,7 @@ def stall():
                     m.d.sync += self.pc.eq(target.addr)
                     m.d.comb += instr.eq(res.instr)
 
-                self.cont(m, data=instr, pc=target.addr, access_fault=fetch_error, rvc=0)
+                self.cont(m, instr=instr, pc=target.addr, access_fault=fetch_error, rvc=0)
 
         @def_method(m, self.verify_branch, ready=stalled)
         def _(from_pc: Value, next_pc: Value):
@@ -210,7 +210,7 @@ def elaborate(self, platform) -> TModule:
                 with m.If(~cache_resp.error):
                     m.d.sync += current_pc.eq(current_pc + Mux(is_rvc, C(2, 3), C(4, 3)))
 
-                self.cont(m, data=instr, pc=current_pc, access_fault=cache_resp.error, rvc=is_rvc)
+                self.cont(m, instr=instr, pc=current_pc, access_fault=cache_resp.error, rvc=is_rvc)
 
         @def_method(m, self.verify_branch, ready=(stalled & ~flushing))
         def _(from_pc: Value, next_pc: Value):

coreblocks/fu/fu_decoder.py

@@ -1,7 +1,7 @@
 from typing import Sequence, Type
 from amaranth import *
 
-from coreblocks.params import GenParams, CommonLayouts
+from coreblocks.params import GenParams, CommonLayoutFields
 
 from enum import IntFlag
 
@@ -19,9 +19,9 @@ class Decoder(Elaboratable):
     """
 
     def __init__(self, gen_params: GenParams, decode_fn: Type[IntFlag], ops: Sequence[tuple], check_optype: bool):
-        layouts = gen_params.get(CommonLayouts)
+        layouts = gen_params.get(CommonLayoutFields)
 
-        self.exec_fn = Record(layouts.exec_fn)
+        self.exec_fn = Record(layouts.exec_fn_layout)
         self.decode_fn = Signal(decode_fn)
         self.ops = ops
         self.check_optype = check_optype

coreblocks/lsu/dummyLsu.py

@@ -204,9 +204,9 @@ def __init__(self, gen_params: GenParams, bus: WishboneMaster) -> None:
         self.fu_layouts = gen_params.get(FuncUnitLayouts)
         self.lsu_layouts = gen_params.get(LSULayouts)
 
-        self.insert = Method(i=self.lsu_layouts.rs_insert_in)
-        self.select = Method(o=self.lsu_layouts.rs_select_out)
-        self.update = Method(i=self.lsu_layouts.rs_update_in)
+        self.insert = Method(i=self.lsu_layouts.rs.insert_in)
+        self.select = Method(o=self.lsu_layouts.rs.select_out)
+        self.update = Method(i=self.lsu_layouts.rs.update_in)
         self.get_result = Method(o=self.fu_layouts.accept)
         self.precommit = Method(i=self.lsu_layouts.precommit)
 
@@ -215,7 +215,7 @@ def __init__(self, gen_params: GenParams, bus: WishboneMaster) -> None:
     def elaborate(self, platform):
         m = TModule()
         reserved = Signal()  # means that current_instr is reserved
-        current_instr = Record(self.lsu_layouts.rs_data_layout + [("valid", 1)])
+        current_instr = Record(self.lsu_layouts.rs.data_layout + [("valid", 1)])
 
         m.submodules.internal = internal = LSUDummyInternals(self.gen_params, self.bus, current_instr)
 
@@ -233,12 +233,12 @@ def _(rs_data: Record, rs_entry_id: Value):
             m.d.sync += current_instr.valid.eq(1)
 
         @def_method(m, self.update)
-        def _(tag: Value, value: Value):
-            with m.If(current_instr.rp_s1 == tag):
-                m.d.sync += current_instr.s1_val.eq(value)
+        def _(reg_id: Value, reg_val: Value):
+            with m.If(current_instr.rp_s1 == reg_id):
+                m.d.sync += current_instr.s1_val.eq(reg_val)
                 m.d.sync += current_instr.rp_s1.eq(0)
-            with m.If(current_instr.rp_s2 == tag):
-                m.d.sync += current_instr.s2_val.eq(value)
+            with m.If(current_instr.rp_s2 == reg_id):
+                m.d.sync += current_instr.s2_val.eq(reg_val)
                 m.d.sync += current_instr.rp_s2.eq(0)
 
         @def_method(m, self.get_result, result_ready)

coreblocks/params/genparams.py

@@ -7,6 +7,7 @@
 from .icache_params import ICacheParameters
 from .fu_params import extensions_supported
 from ..peripherals.wishbone import WishboneParameters
+from transactron.utils import make_hashable
 
 from typing import TYPE_CHECKING
 
@@ -35,10 +36,11 @@ class DependentCache:
     """
 
     def __init__(self):
-        self._depcache: dict[tuple[Type, frozenset[tuple[str, Any]]], Type] = {}
+        self._depcache: dict[tuple[Type, Any], Type] = {}
 
     def get(self, cls: Type[T], **kwargs) -> T:
-        v = self._depcache.get((cls, frozenset(kwargs.items())), None)
+        cache_key = make_hashable(kwargs)
+        v = self._depcache.get((cls, cache_key), None)
         if v is None:
             positional_count = cls.__init__.__code__.co_argcount
 
@@ -50,7 +52,7 @@ def get(self, cls: Type[T], **kwargs) -> T:
                 v = cls(self, **kwargs)
             else:
                 v = cls(**kwargs)
-            self._depcache[(cls, frozenset(kwargs.items()))] = v
+            self._depcache[(cls, cache_key)] = v
         return v