Merge branch 'master' into mtvec-vectored-mode

.github/workflows/benchmark.yml

@@ -36,9 +36,6 @@ jobs:
           # https://github.com/actions/runner/issues/2033
           chown -R $(id -u):$(id -g) $PWD
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -114,9 +111,6 @@ jobs:
           # https://github.com/actions/runner/issues/2033
           chown -R $(id -u):$(id -g) $PWD
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -165,9 +159,6 @@ jobs:
           # https://github.com/actions/runner/issues/2033
           chown -R $(id -u):$(id -g) $PWD
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:

.github/workflows/deploy_gh_pages.yml

@@ -23,9 +23,6 @@ jobs:
       - name: Checkout
         uses: actions/checkout@v4
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:

.github/workflows/main.yml

@@ -20,9 +20,6 @@ jobs:
       - name: Checkout
         uses: actions/checkout@v4
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -153,9 +150,6 @@ jobs:
           git config --global --add safe.directory /__w/coreblocks/coreblocks
           git submodule > .gitmodules-hash
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -263,9 +257,6 @@ jobs:
           git config --global --add safe.directory /__w/coreblocks/coreblocks
           git submodule > .gitmodules-hash
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -318,9 +309,6 @@ jobs:
       - name: Checkout
         uses: actions/checkout@v4
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
@@ -353,9 +341,6 @@ jobs:
       - name: Checkout
         uses: actions/checkout@v4
 
-      - name: Checkout submodules
-        run: git submodule update --init --recursive amaranth-stubs
-
       - name: Set up Python
         uses: actions/setup-python@v5
         with:

.gitmodules

@@ -8,6 +8,3 @@
 [submodule "test/external/riscof/riscv-arch-test"]
 	path = test/external/riscof/riscv-arch-test
 	url = https://github.com/riscv-non-isa/riscv-arch-test.git
-[submodule "amaranth-stubs"]
-	path = amaranth-stubs
-	url = https://github.com/kuznia-rdzeni/amaranth-stubs.git

README.md

@@ -9,7 +9,7 @@ Coreblocks is an experimental, modular out-of-order [RISC-V](https://riscv.org/s
  * Simplicity. Coreblocks is an academic project, accessible to students.
    It should be suitable for teaching essentials of out-of-order architectures.
  * Modularity. We want to be able to easily experiment with the core by adding, replacing and modifying modules without changing the source too much.
-   For this goal, we designed a [transaction system](https://kuznia-rdzeni.github.io/coreblocks/Transactions.html) inspired by [Bluespec](http://wiki.bluespec.com/).
+   For this goal, we designed a transaction system called [Transactron](https://github.com/kuznia-rdzeni/transactron), which is inspired by [Bluespec](http://wiki.bluespec.com/).
  * Fine-grained testing. Outside of the integration tests for the full core, modules are tested individually.
    This is to support an agile style of development.
 
@@ -25,9 +25,6 @@ The core currently supports the full RV32I instruction set and several extension
 Exceptions and some of machine-mode CSRs are supported, the support for interrupts is currently rudimentary and incompatible with the RISC-V spec.
 Coreblocks can be used with [LiteX](https://github.com/enjoy-digital/litex) (currently using a [patched version](https://github.com/kuznia-rdzeni/litex/tree/coreblocks)).
 
-The transaction system we use as the foundation for the core is well-tested and usable.
-We plan to make it available as a separate Python package.
-
 ## Documentation
 
 The [documentation for our project](https://kuznia-rdzeni.github.io/coreblocks/) is automatically generated using [Sphinx](https://www.sphinx-doc.org/).

coreblocks/core.py

@@ -1,11 +1,11 @@
 from amaranth import *
-from amaranth.lib.wiring import Component, flipped, connect, Out
+from amaranth.lib.wiring import Component, flipped, connect, In, Out
 from transactron.utils.amaranth_ext.elaboratables import ModuleConnector
 
 from transactron.utils.dependencies import DependencyContext
 from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
 from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
-from coreblocks.priv.traps.interrupt_controller import InternalInterruptController
+from coreblocks.priv.traps.interrupt_controller import ISA_RESERVED_INTERRUPTS, InternalInterruptController
 from transactron.core import Transaction, TModule
 from transactron.lib import ConnectTrans, MethodProduct
 from coreblocks.interface.layouts import *
@@ -35,12 +35,14 @@
 class Core(Component):
     wb_instr: WishboneInterface
     wb_data: WishboneInterface
+    interrupts: Signal
 
     def __init__(self, *, gen_params: GenParams):
         super().__init__(
             {
                 "wb_instr": Out(WishboneSignature(gen_params.wb_params)),
                 "wb_data": Out(WishboneSignature(gen_params.wb_params)),
+                "interrupts": In(ISA_RESERVED_INTERRUPTS + gen_params.interrupt_custom_count),
             }
         )
 
@@ -96,8 +98,8 @@ def __init__(self, *, gen_params: GenParams):
     def elaborate(self, platform):
         m = TModule()
 
-        connect(m, flipped(self.wb_instr), self.wb_master_instr.wb_master)
-        connect(m, flipped(self.wb_data), self.wb_master_data.wb_master)
+        connect(m.top_module, flipped(self.wb_instr), self.wb_master_instr.wb_master)
+        connect(m.top_module, flipped(self.wb_data), self.wb_master_data.wb_master)
 
         m.submodules.wb_master_instr = self.wb_master_instr
         m.submodules.wb_master_data = self.wb_master_data
@@ -115,6 +117,8 @@ def elaborate(self, platform):
 
         m.submodules.csr_generic = self.csr_generic
         m.submodules.interrupt_controller = self.interrupt_controller
+        m.d.comb += self.interrupt_controller.internal_report_level.eq(self.interrupts[0:16])
+        m.d.comb += self.interrupt_controller.custom_report.eq(self.interrupts[16:])
 
         m.submodules.core_counter = core_counter = CoreInstructionCounter(self.gen_params)
 
@@ -136,10 +140,12 @@ def elaborate(self, platform):
 
         m.submodules.exception_information_register = self.exception_information_register
 
-        fetch_resume_fb, fetch_resume_unifiers = self.connections.get_dependency(FetchResumeKey())
-        m.submodules.fetch_resume_unifiers = ModuleConnector(**fetch_resume_unifiers)
+        fetch_resume = self.connections.get_optional_dependency(FetchResumeKey())
+        if fetch_resume is not None:
+            fetch_resume_fb, fetch_resume_unifiers = fetch_resume
+            m.submodules.fetch_resume_unifiers = ModuleConnector(**fetch_resume_unifiers)
 
-        m.submodules.fetch_resume_connector = ConnectTrans(fetch_resume_fb, self.frontend.resume_from_unsafe)
+            m.submodules.fetch_resume_connector = ConnectTrans(fetch_resume_fb, self.frontend.resume_from_unsafe)
 
         m.submodules.announcement = self.announcement
         m.submodules.func_blocks_unifier = self.func_blocks_unifier

coreblocks/core_structs/rob.py

@@ -1,5 +1,4 @@
 from amaranth import *
-from amaranth.lib.data import View
 import amaranth.lib.memory as memory
 from transactron import Method, Transaction, def_method, TModule
 from transactron.lib.metrics import *
@@ -19,7 +18,7 @@ def __init__(self, gen_params: GenParams) -> None:
         self.retire = Method()
         self.done = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
         self.exception = Array(Signal() for _ in range(2**self.params.rob_entries_bits))
-        self.data = memory.Memory(shape=layouts.data_layout.size, depth=2**self.params.rob_entries_bits, init=[])
+        self.data = memory.Memory(shape=layouts.data_layout, depth=2**self.params.rob_entries_bits, init=[])
         self.get_indices = Method(o=layouts.get_indices, nonexclusive=True)
 
         self.perf_rob_wait_time = FIFOLatencyMeasurer(
@@ -54,8 +53,8 @@ def elaborate(self, platform):
 
         @def_method(m, self.peek, ready=peek_possible)
         def _():
-            return {  # remove View after Amaranth upgrade
-                "rob_data": View(self.params.get(ROBLayouts).data_layout, read_port.data),
+            return {
+                "rob_data": read_port.data,
                 "rob_id": start_idx,
                 "exception": self.exception[start_idx],
             }

coreblocks/frontend/fetch/fetch.py

@@ -402,7 +402,13 @@ def _():
         if self.gen_params.extra_verification:
             expect_unstall_unsafe = Signal()
             prev_stalled_unsafe = Signal()
-            unifier_ready = DependencyContext.get().get_dependency(FetchResumeKey())[0].ready
+            dependencies = DependencyContext.get()
+            fetch_resume = dependencies.get_optional_dependency(FetchResumeKey())
+            if fetch_resume is not None:
+                unifier_ready = fetch_resume[0].ready
+            else:
+                unifier_ready = C(0)
+
             m.d.sync += prev_stalled_unsafe.eq(stalled_unsafe)
             with m.FSM("running"):
                 with m.State("running"):

coreblocks/frontend/frontend.py

@@ -62,7 +62,7 @@ def __init__(self, *, gen_params: GenParams, instr_bus: BusMasterInterface):
     def elaborate(self, platform):
         m = TModule()
 
-        if self.icache_refiller:
+        if self.gen_params.icache_params.enable:
             m.submodules.icache_refiller = self.icache_refiller
         m.submodules.icache = self.icache
 

coreblocks/func_blocks/fu/fpu/fpu_common.py

@@ -0,0 +1,38 @@
+from amaranth.lib import enum
+
+
+class RoundingModes(enum.Enum):
+    ROUND_UP = 3
+    ROUND_DOWN = 2
+    ROUND_ZERO = 1
+    ROUND_NEAREST_EVEN = 0
+    ROUND_NEAREST_AWAY = 4
+
+
+class Errors(enum.IntFlag):
+    INVALID_OPERATION = enum.auto()
+    DIVISION_BY_ZERO = enum.auto()
+    OVERFLOW = enum.auto()
+    UNDERFLOW = enum.auto()
+    INEXACT = enum.auto()
+
+
+class FPUParams:
+    """FPU parameters
+
+    Parameters
+    ----------
+    sig_width: int
+        Width of significand, including implicit bit
+    exp_width: int
+        Width of exponent
+    """
+
+    def __init__(
+        self,
+        *,
+        sig_width: int = 24,
+        exp_width: int = 8,
+    ):
+        self.sig_width = sig_width
+        self.exp_width = exp_width