Config changes

kuznia-rdzeni · Nov 19, 2024 · e85081a · e85081a
1 parent ab01b5f
commit e85081a
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Showing 2 changed files with 13 additions and 4 deletions.
diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py
@@ -32,6 +32,13 @@
         [ALUComponent(), ShiftUnitComponent(), JumpComponent(), ExceptionUnitComponent(), PrivilegedUnitComponent()],
         rs_entries=4,
     ),
+    RSBlockComponent(
+        [
+            MulComponent(mul_unit_type=MulType.SEQUENCE_MUL),
+            DivComponent(),
+        ],
+        rs_entries=2,
+    ),
     RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS),
     CSRBlockComponent(),
 )
@@ -139,7 +146,9 @@ def __post_init__(self):
     _implied_extensions: Extension = Extension(0)
     _generate_test_hardware: bool = False
 
-    pma: list[PMARegion] = field(default_factory=list)
+    pma: list[PMARegion] = field(
+        default_factory=lambda: [PMARegion(0xE0000000, 0xFFFFFFFF, mmio=True)]
+    )  # defult I/O region used in LiteX coreblocks
 
 
 class CoreConfiguration(_CoreConfigurationDataClass):

diff --git a/test/params/test_configurations.py b/test/params/test_configurations.py
@@ -18,9 +18,9 @@ class ISAStrTest:
     TEST_CASES = [
         ISAStrTest(
             basic_core_config,
-            "rv32izicsr_zifencei_xintmachinemode",
-            "rv32izicsr_zifencei_xintmachinemode",
-            "rv32izicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
         ),
         ISAStrTest(
             full_core_config,