External interrupt interface

kuznia-rdzeni · Nov 19, 2024 · ab01b5f · ab01b5f
1 parent c19fcfe
commit ab01b5f
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/coreblocks/core.py b/coreblocks/core.py
@@ -1,5 +1,5 @@
 from amaranth import *
-from amaranth.lib.wiring import Component, flipped, connect, Out
+from amaranth.lib.wiring import Component, flipped, connect, In, Out
 from transactron.utils.amaranth_ext.elaboratables import ModuleConnector
 
 from transactron.utils.dependencies import DependencyContext
@@ -35,12 +35,14 @@
 class Core(Component):
     wb_instr: WishboneInterface
     wb_data: WishboneInterface
+    interrupts: Signal
 
     def __init__(self, *, gen_params: GenParams):
         super().__init__(
             {
                 "wb_instr": Out(WishboneSignature(gen_params.wb_params)),
                 "wb_data": Out(WishboneSignature(gen_params.wb_params)),
+                "interrupts": In(gen_params.isa.xlen),
             }
         )
 
@@ -115,6 +117,8 @@ def elaborate(self, platform):
 
         m.submodules.csr_generic = self.csr_generic
         m.submodules.interrupt_controller = self.interrupt_controller
+        m.d.comb += self.interrupt_controller.internal_report_level.eq(self.interrupts[0:16])
+        m.d.comb += self.interrupt_controller.custom_report.eq(self.interrupts[16:])
 
         m.submodules.core_counter = core_counter = CoreInstructionCounter(self.gen_params)
 

diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py
@@ -127,7 +127,7 @@ def __post_init__(self):
 
     instr_buffer_size: int = 4
 
-    interrupt_custom_count: int = 0
+    interrupt_custom_count: int = 16
     interrupt_custom_edge_trig_mask: int = 0
 
     user_mode: bool = True