Format

test/transactions/test_transaction_lib.py

@@ -132,14 +132,15 @@ def process():
         with self.run_simulation(m) as sim:
             sim.add_sync_process(process)
 
+
 class MemoryReproduce(TestCaseWithSimulator):
     class DUT(Elaboratable):
         def __init__(self):
             pass
 
         def elaborate(self, platform):
-            m=Module()
-            self.mem = Memory(width = 8, depth = 8)
+            m = Module()
+            self.mem = Memory(width=8, depth=8)
             m.submodules.read_port = self.read_port = self.mem.read_port()
             m.submodules.write_port = self.write_port = self.mem.write_port()
             return m
@@ -169,8 +170,6 @@ def process():
             sim.add_sync_process(process)
 
 
-
-
 class TestMemoryBank(TestCaseWithSimulator):
     test_conf = [(9, 3, 3, 3, 14), (16, 1, 1, 3, 15), (16, 1, 1, 1, 16), (12, 3, 1, 1, 17)]
 
@@ -228,7 +227,7 @@ def reader_resp():
                 d = read_req_queue.popleft()
                 print("read_resp", d)
                 yield from m.read_resp.call()
-                #self.assertEqual((yield from m.read_resp.call()), {"data": d})
+                # self.assertEqual((yield from m.read_resp.call()), {"data": d})
                 yield from random_wait(reader_resp_rand)
 
         def internal_reader_resp():