Example to reproduce amaranth bug.

kuznia-rdzeni · Oct 1, 2023 · b87149b · b87149b
1 parent 17d0f14
commit b87149b
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Showing 2 changed files with 48 additions and 4 deletions.
diff --git a/coreblocks/structs_common/exception.py b/coreblocks/structs_common/exception.py
@@ -72,7 +72,7 @@ def _(cause, rob_id):
                 diff2 = Signal.like(rob_start_idx)
                 m.d.comb += diff1.eq((rob_id - rob_start_idx))
                 m.d.comb += diff2.eq((self.rob_id - rob_start_idx))
-                m.d.comb += should_write.eq(diff1<diff2)
+                m.d.comb += should_write.eq(diff1 < diff2)
             with m.Else():
                 m.d.comb += should_write.eq(1)
 

diff --git a/test/transactions/test_transaction_lib.py b/test/transactions/test_transaction_lib.py
@@ -132,6 +132,44 @@ def process():
         with self.run_simulation(m) as sim:
             sim.add_sync_process(process)
 
+class MemoryReproduce(TestCaseWithSimulator):
+    class DUT(Elaboratable):
+        def __init__(self):
+            pass
+
+        def elaborate(self, platform):
+            m=Module()
+            self.mem = Memory(width = 8, depth = 8)
+            m.submodules.read_port = self.read_port = self.mem.read_port()
+            m.submodules.write_port = self.write_port = self.mem.write_port()
+            return m
+
+    def test_minimal(self):
+        m = self.DUT()
+
+        def process():
+            yield m.read_port.addr.eq(1)
+            yield m.read_port.en.eq(1)
+            yield
+            print((yield m.read_port.data))
+            yield
+            yield m.write_port.addr.eq(2)
+            yield m.write_port.data.eq(14)
+            yield m.write_port.en.eq(1)
+            print((yield m.read_port.data))
+            yield
+            yield m.write_port.en.eq(0)
+            print((yield m.read_port.data))
+            yield
+            print((yield m.read_port.data))
+            yield
+            print((yield m.read_port.data))
+
+        with self.run_simulation(m) as sim:
+            sim.add_sync_process(process)
+
+
+
 
 class TestMemoryBank(TestCaseWithSimulator):
     test_conf = [(9, 3, 3, 3, 14), (16, 1, 1, 3, 15), (16, 1, 1, 1, 16), (12, 3, 1, 1, 17)]
@@ -160,31 +198,37 @@ def writer():
             for i in range(test_count):
                 d = random.randrange(2**data_width)
                 a = random.randrange(max_addr)
+                print("write pocz", a, d)
                 yield from m.write.call(data=d, addr=a)
                 for i in range(2):
                     yield Settle()
+                print("write kon")
                 data_dict[a] = d
                 yield from random_wait(writer_rand)
 
         def reader_req():
-            for i in range(test_count):
+            for cycle in range(test_count):
                 a = random.randrange(max_addr)
+                print("read_req pocz", a)
                 yield from m.read_req.call(addr=a)
                 for i in range(1):
                     yield Settle()
+                print("read_req kon")
                 if safe_writes:
                     d = data_dict[a]
                     read_req_queue.append(d)
                 else:
-                    addr_queue.append((i, a))
+                    addr_queue.append((cycle, a))
                 yield from random_wait(reader_req_rand)
 
         def reader_resp():
             for i in range(test_count):
                 while not read_req_queue:
                     yield from random_wait(reader_resp_rand)
                 d = read_req_queue.popleft()
-                self.assertEqual((yield from m.read_resp.call()), {"data": d})
+                print("read_resp", d)
+                yield from m.read_resp.call()
+                #self.assertEqual((yield from m.read_resp.call()), {"data": d})
                 yield from random_wait(reader_resp_rand)
 
         def internal_reader_resp():