DummyLSU as a FU #2606
tilkmain.yml
on: pull_request
Synthesize full core
32s
Build regression tests (riscv-tests)
50s
Build regression tests (riscv-arch-test)
44s
Run unit tests
8m 21s
Check code formatting and typing
33s
Run regression tests (riscv-tests)
3m 10s
Run regression tests (riscv-arch-test)
12m 50s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
385 KB |
|