Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

DummyLSU as a FU #635

Merged
merged 18 commits into from
Apr 3, 2024
Merged

DummyLSU as a FU #635

merged 18 commits into from
Apr 3, 2024

Conversation

tilk
Copy link
Member

@tilk tilk commented Mar 29, 2024

Oops, I did it again. DummyLSU is now smaller, faster, and a FU. As this LSU is still dumb, FifoRS is used to maintain the instruction ordering. Still, having an actual RS for LSU allows for more latency hiding for memory requests.

Depends on #634. Fixes #591.

TODO:

  • Move DummyLSU to fu directory.
  • Fix tests.

@tilk tilk added enhancement New feature or request optimization This is *just* an optimization! labels Mar 29, 2024
@tilk tilk added this to the Improve the core's performance milestone Mar 29, 2024
@tilk tilk marked this pull request as ready for review April 2, 2024 10:47
@tilk tilk force-pushed the tilk/fu-dummylsu branch from 5c3bf3d to b0ef7df Compare April 2, 2024 11:20
@@ -180,7 +164,8 @@ def generate_instr(self, max_reg_val, max_imm_val):
}
)

self.exception_result.append(
print(f"addr:0x{addr:08x} misaligned:{misaligned} bus_err:{bus_err}")
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this print intentional?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is probably a leftover from debugging, will remove.

@tilk tilk requested review from xThaid and piotro888 April 3, 2024 08:21
@tilk tilk merged commit bfdfea0 into master Apr 3, 2024
8 checks passed
@tilk tilk deleted the tilk/fu-dummylsu branch April 3, 2024 09:30
github-actions bot pushed a commit that referenced this pull request Apr 3, 2024
* Refactor RS, implement FifoRS

* New RS test

* Test FifoRS and fix bugs

* Lint

* Derive from RSBase

* Workaround for Amaranth issue with Signal(range(1))

* First try

* Fix bug

* Try to break up critical path

* Lint

* LSU test, fix buuuugs

* Fix PMA test

* Move LSU

* Remove debug print

---------

Co-authored-by: lekcyjna123 <[email protected]>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request optimization This is *just* an optimization!
Projects
None yet
Development

Successfully merging this pull request may close these issues.

More RS slots in DummyLSU load/store unit
3 participants