Refactor RISC-V instruction models #2561
xThaidmain.yml
on: pull_request
Synthesize full core
30s
Build regression tests (riscv-tests)
48s
Build regression tests (riscv-arch-test)
48s
Run unit tests
6m 25s
Check code formatting and typing
36s
Run regression tests (riscv-tests)
3m 46s
Run regression tests (riscv-arch-test)
11m 52s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
324 KB |
|