Refactor RISC-V instruction models #2558
xThaidmain.yml
on: pull_request
Synthesize full core
34s
Build regression tests (riscv-tests)
48s
Build regression tests (riscv-arch-test)
54s
Run unit tests
6m 6s
Check code formatting and typing
17s
Run regression tests (riscv-tests)
4m 2s
Run regression tests (riscv-arch-test)
11m 42s
Annotations
1 error
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Check code formatting and typing
Process completed with exit code 1.
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Artifacts
Produced during runtime
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verilog-full-core
Expired
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324 KB |
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