DummyLSU as a FU #2552
main.yml
on: pull_request
Synthesize full core
31s
Build regression tests (riscv-tests)
47s
Build regression tests (riscv-arch-test)
44s
Run unit tests
4m 34s
Check code formatting and typing
32s
Run regression tests (riscv-tests)
4m 14s
Run regression tests (riscv-arch-test)
12m 35s
Annotations
2 errors
Check code formatting and typing
Process completed with exit code 1.
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Run unit tests
Process completed with exit code 1.
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Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verilog-full-core
Expired
|
339 KB |
|