Refactor RISC-V instruction models #2544
xThaidmain.yml
on: pull_request
Synthesize full core
28s
Build regression tests (riscv-tests)
43s
Build regression tests (riscv-arch-test)
42s
Run unit tests
6m 27s
Check code formatting and typing
34s
Run regression tests (riscv-tests)
4m 22s
Run regression tests (riscv-arch-test)
11m 52s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
323 KB |
|