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Refactor RISC-V instruction models #2537

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Refactor RISC-V instruction models

Refactor RISC-V instruction models #2537

Triggered via pull request March 27, 2024 15:49
@xThaidxThaid
synchronize #631
xThaid:instr_def_refactor
Status Failure
Total duration 13m 10s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
40s
Synthesize full core
Build regression tests (riscv-tests)
52s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
49s
Build regression tests (riscv-arch-test)
Run unit tests
5m 27s
Run unit tests
Check code formatting and typing
36s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 58s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 2s
Run regression tests (riscv-arch-test)
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1 error
Run unit tests
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
verilog-full-core Expired
323 KB