Synchronous register file using MemoryBank #3120
main.yml
on: pull_request
Synthesize full core
36s
Build regression tests (riscv-tests)
46s
Build regression tests (riscv-arch-test)
42s
Run unit tests
6m 35s
Check code formatting and typing
44s
Run regression tests (riscv-tests)
4m 40s
Run regression tests (riscv-arch-test)
14m 28s
Annotations
7 warnings
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verilog-full-core
|
548 KB |
|