Synchronous register file using MemoryBank

[tilk]

This PR implements a synchronous register file. Read requests are done on RS selection, results are read, like previously, on RS insertion. The change will enable using FPGA Block RAMs and multiport RAM structures utilizing block RAMs.

Closes #737.

TODO:

• Merge Transactron PR Expose internal memory in memory banks transactron#18, change commit in dependencies.

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417 (0.000)	0.513 (0.000)	0.337 (0.000)	0.655 (0.000)	0.361 (0.000)	0.290 (0.000)	0.326 (0.000)	0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▲ 14290 (+621)	▲ 4365 (+102)	▲ 1490 (+32)	▼ 1196 (-256)	▼ 51 (-2)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 21518 (-4972)	▲ 6980 (+102)	▲ 1852 (+32)	▼ 1248 (-256)	▲ 43 (+3)

[piotro888]

lgtm

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417 (0.000)	0.513 (0.000)	0.337 (0.000)	0.655 (0.000)	0.361 (0.000)	0.290 (0.000)	0.326 (0.000)	0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▲ 14066 (+397)	▲ 4365 (+102)	▲ 1490 (+32)	▼ 1196 (-256)	▲ 54 (+1)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 20801 (-5689)	▲ 6980 (+102)	▲ 1852 (+32)	▼ 1248 (-256)	▲ 45 (+5)

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417 (0.000)	0.513 (0.000)	0.337 (0.000)	0.655 (0.000)	0.361 (0.000)	0.290 (0.000)	0.326 (0.000)	0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 14410 (-3318)	▲ 4365 (+102)	1458 (0)	▼ 1196 (-256)	▲ 52 (+5)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 20703 (-1315)	▲ 6980 (+102)	▲ 1852 (+32)	▼ 1248 (-256)	▲ 44 (+0)