mtvec vectored mode #3073
main.yml
on: pull_request
Synthesize full core
33s
Build regression tests (riscv-tests)
43s
Build regression tests (riscv-arch-test)
47s
Run unit tests
14m 45s
Check code formatting and typing
36s
Run regression tests (riscv-tests)
5m 37s
Run regression tests (riscv-arch-test)
14m 33s
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verilog-full-core
|
539 KB |
|