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mtvec vectored mode #3073

mtvec vectored mode

mtvec vectored mode #3073

Triggered via pull request November 19, 2024 10:45
Status Success
Total duration 15m 37s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
33s
Synthesize full core
Build regression tests (riscv-tests)
43s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
47s
Build regression tests (riscv-arch-test)
Run unit tests
14m 45s
Run unit tests
Check code formatting and typing
36s
Check code formatting and typing
Run regression tests (riscv-tests)
5m 37s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
14m 33s
Run regression tests (riscv-arch-test)
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Artifacts

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Name Size
verilog-full-core
539 KB