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Multiport MemoryBank #3001

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Multiport MemoryBank

Multiport MemoryBank #3001

Triggered via pull request October 31, 2024 09:41
@tilktilk
synchronize #736
tilk/multiport-memorybanks
Status Success
Total duration 13m 55s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
27s
Synthesize full core
Build regression tests (riscv-tests)
47s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
48s
Build regression tests (riscv-arch-test)
Run unit tests
7m 34s
Run unit tests
Check code formatting and typing
37s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 43s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 47s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
verilog-full-core
362 KB