Multiport MemoryBank
#736
Merged
Multiport MemoryBank
#736
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
lekcyjna123
approved these changes
Oct 21, 2024
kalinf
approved these changes
Oct 30, 2024
tilk
force-pushed
the
tilk/multiport-memorybanks
branch
from
2c8a77d to
9c84fe7
Compare
tilk
added a commit
to kuznia-rdzeni/transactron
that referenced
this pull request
Nov 25, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
In preparation for superscalarity support, this PR extends Transactron's
MemoryBankandAsyncMemoryBankwith support for multiple read and write ports.