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17 Open 7 Closed
17 Open 7 Closed
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Issues list

Unrecognised nodes
#29 opened Apr 20, 2022 by jameshanlon
Add support for specifying only through points as waypoints enhancement New feature or request
#28 opened Mar 12, 2022 by jameshanlon
Investigate alternative wildcard matching algorithm enhancement New feature or request refactoring
#25 opened Feb 25, 2022 by jameshanlon
Introduce more exception types enhancement New feature or request refactoring
#23 opened Feb 20, 2022 by jameshanlon
Run tests with Clang sanitizers enhancement New feature or request
#22 opened Feb 19, 2022 by jameshanlon
Tidy headers with include what you use refactoring
#21 opened Feb 19, 2022 by jameshanlon
Add support for bitwise connectivity enhancement New feature or request
#20 opened Feb 19, 2022 by jameshanlon
Consider using magic_enum refactoring
#19 opened Feb 14, 2022 by jameshanlon
Add a facility to compile Verilog from a string enhancement New feature or request
#18 opened Feb 12, 2022 by jameshanlon
Improve dotfile dump with better annotations enhancement New feature or request
#17 opened Feb 8, 2022 by jameshanlon
Verilator cannot inline interfaces bug Something isn't working
#16 opened Feb 8, 2022 by jameshanlon
Add option to dump named start/end points for fainin/fanout queries enhancement New feature or request
#15 opened Feb 8, 2022 by jameshanlon
Don’t list internal verilator nodes in reports enhancement New feature or request
#14 opened Feb 8, 2022 by jameshanlon
Self paths bug Something isn't working
#11 opened Feb 8, 2022 by jameshanlon
2
Performance issues with large graphs enhancement New feature or request
#6 opened Jul 26, 2021 by jameshanlon
Register identification should check for sensitivity to a clock edge enhancement New feature or request
#5 opened Jul 24, 2021 by jameshanlon
Consider supporting Verible or Surelog as alternative to Verilator enhancement New feature or request
#3 opened May 4, 2021 by mithro
1
ProTip! Updated in the last three days: updated:>2024-11-12.