Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add a facility to compile Verilog from a string #18

Open
jameshanlon opened this issue Feb 12, 2022 · 0 comments
Open

Add a facility to compile Verilog from a string #18

jameshanlon opened this issue Feb 12, 2022 · 0 comments
Labels
enhancement New feature or request

Comments

@jameshanlon
Copy link
Owner

So that Verilog code can be defined inline in unit tests.
@jameshanlon jameshanlon added the enhancement New feature or request label Feb 12, 2022
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
enhancement New feature or request
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@jameshanlon