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v0.14: Added KV maps and VHDL export
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@hneemann hneemann released this 31 Aug 14:42
· 2641 commits to master since this release
v0.14
725b590 
- Added visualization of KV maps (thanks to roy77)
- Added VHDL export
  (Not yet complete, but the example processor is running on a FPGA.)
- Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
- Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode
  clock manager (MMCM) is used if clock frequency exceeds 37kHz)
- Added shortcut 'B' which sets the number of data bits in all selected components.
- Breaking changes:
  - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.
    As a consequence of that the address bits settings in RAMs and ROMs
    are lost. To fix that, reset the number of address bits.
  - Added an enable input to the counter component. If you had used the counter in the
    past you have to set the en input to 1. The function of the overflow output also
    has changed (see tooltip) and now allows the cascading of counters.
  - XOR now can have more than two inputs. If you had used the XOR gate with inverted
    inputs, you have to reselect the inputs to invert.
- Some minor bug fixes.
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