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Integrate ALU into CPU.
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codecyang committed Jun 19, 2020
1 parent a213bac commit 873cc68
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35 changes: 28 additions & 7 deletions src/verilog/Computer.v
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Expand Up @@ -2,10 +2,8 @@
* Changed from: https://github.com/cccbook/co/blob/master/code/verilog/nand2tetris/computer.v
*/

`include "alu.v"

module CPU(output writeM, output[15:0] outM, output[14:0] addressM,pc, input clk,reset, input[15:0] inM,I);
wire[15:0] Ain, Aout, AorM, ALUout, Dout, addressMOut;
wire[15:0] Aout, AorM, ALUout, Dout;

reg[15:0] A, D, pcReg;
assign Aout = A;
Expand All @@ -24,7 +22,31 @@ module CPU(output writeM, output[15:0] outM, output[14:0] addressM,pc, input clk
// 16-bit ALU.
assign AorM = I[12] ? inM : Aout;

ALU16 alu(ALUout, zr, ng, Dout, AorM, I[11], I[10], I[9], I[8], I[7], I[6]);
// I[11], x = 0
wire[15:0] zx = I[11] ? 16'b0 : Dout;

// I[10], x = ~x
wire[15:0] nx = I[10] ? ~zx : zx;

// I[9], y = 0
wire[15:0] zy = I[9] ? 16'b0 : AorM;

// I[8], y = !y
wire[15:0] ny = I[8] ? ~zy : zy;

// I[7] = 0, ALUout = x & y
// I[7] = 1, ALUout = x + y
wire[15:0] f = I[7] ? nx + ny : nx & ny;

// I[6] = 0, ALUout = f
// I[6] = 1, ALUout = ~f
assign ALUout = I[6] ? ~f : f;

// ALUout = 0, zr = 1
wire zr = ALUout == 0;

// ALUout < 0, ng = 1
wire ng = ALUout[15];

// output
assign addressM = Aout[14:0];
Expand All @@ -35,14 +57,13 @@ module CPU(output writeM, output[15:0] outM, output[14:0] addressM,pc, input clk
wire Atype = ~I[15]; // A-instruction
wire AluToA = I[15] & I[5]; // AluToA = I[15] & d1
wire Aload = Atype | AluToA; // A-instruction or data load to A-register
assign Ain = AluToA ? ALUout : I;

// Data register.
wire Dload = I[15] & I[4]; // Dload = I[15] & d2

always @ (posedge clk) begin
// Registers
if(Aload) A = Ain;
if(Aload) A = AluToA ? ALUout : I;
if(Dload) D = ALUout;

// Program Counter.
Expand Down Expand Up @@ -73,7 +94,7 @@ module Computer(input clk, reset);
wire[15:0] inM, outM, I;
wire[14:0] addressM, pc;

Memory ram(inM, clk, writeM, outM, addressM);
ROM32K rom(I, pc);
CPU cpu(writeM, outM, addressM,pc, clk,reset, inM,I);
Memory ram(inM, clk, writeM, outM, addressM);
endmodule // Computer.
10 changes: 0 additions & 10 deletions src/verilog/README.md
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Expand Up @@ -3,7 +3,6 @@
Here are some shortcut to test the chip component.

* [Compile & Test](#compile--test)
* [ALU (16-bit)](#alu-16-bit)
* [CPU (Central Processing Unit)](#cpu-central-processing-unit)
* [Memory](#memory)
* [ROM32K](#rom32k)
Expand All @@ -28,15 +27,6 @@ gtkwave tb_sample.vcd # See graphical wave output.
Under "src/verilog" directory.


### ALU (16-bit)

```
iverilog -o tb_alu.vvp tb_alu.v
vvp tb_alu.vvp
gtkwave tb_alu.vcd
```


### CPU (Central Processing Unit)
> Reference from [cccbook](https://github.com/cccbook/co/blob/1c86da267d19d5e2ec1b5e2dfcb6f53cac2cf74e/code/verilog/nand2tetris/computer.v#L18)
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36 changes: 0 additions & 36 deletions src/verilog/alu.v

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39 changes: 0 additions & 39 deletions src/verilog/tb_alu.v

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