Remove PC.

src/verilog/Computer.v

@@ -3,14 +3,14 @@
  */
 
 `include "alu.v"
-`include "memory.v"
 
 module CPU(output writeM, output[15:0] outM, output[14:0] addressM,pc, input clk,reset, input[15:0] inM,I);
-    wire[15:0] Ain, Aout, AorM, ALUout, Dout, pcOut, addressMOut;
+    wire[15:0] Ain, Aout, AorM, ALUout, Dout, addressMOut;
 
-    reg[15:0] A, D;
+    reg[15:0] A, D, pcReg;
     assign Aout = A;
     assign Dout = D;
+    assign pc = pcReg[14:0];
 
     // PC load.
     wire g = ~(ng | zr);            // g = out > 0 = !(ng|zr)
@@ -19,35 +19,39 @@ module CPU(output writeM, output[15:0] outM, output[14:0] addressM,pc, input clk
     wire passGT = g & I[0];         // gGT = (g&GT) = out > 0
     wire passLE = passLT | passEQ;  // out <= 0
     wire pass = passLE | passGT;    // out <=> 0
-
     wire PCload = I[15] & pass;     // PCload = I15&J
 
     // 16-bit ALU.
     assign AorM = I[12] ? inM : Aout;
 
     ALU16 alu(ALUout, zr, ng, Dout, AorM, I[11], I[10], I[9], I[8], I[7], I[6]);
 
-    PC pc0(pcOut, clk, 1'b1, PCload, reset, Aout);
-    assign pc = pcOut[14:0];
+    // output
+    assign addressM = Aout[14:0];
+    wire writeM = I[15] & I[3];  // writeM = I[15] & d3
+    assign outM = ALUout;
 
     // Address register.
     wire Atype = ~I[15];          // A-instruction
     wire AluToA = I[15] & I[5];   // AluToA = I[15] & d1
     wire Aload = Atype | AluToA;  // A-instruction or data load to A-register
-
     assign Ain = AluToA ? ALUout : I;
 
     // Data register.
     wire Dload = I[15] & I[4];  // Dload = I[15] & d2
 
-    // output
-    assign addressM = Aout[14:0];
-    wire writeM = I[15] & I[3];  // writeM = I[15] & d3
-    assign outM = ALUout;
-
     always @ (posedge clk) begin
+        // Registers
         if(Aload)  A = Ain;
         if(Dload)  D = ALUout;
+
+        // Program Counter.
+        if(reset)
+            pcReg = 16'b0;
+        else if(PCload)
+            pcReg = Aout;
+        else
+            pcReg = pcReg + 1'b1;
     end
 endmodule  // CPU.
 
@@ -60,6 +64,11 @@ module Memory(output[15:0] out, input clk,load, input[15:0] in, input[14:0] addr
     end
 endmodule  // Memory.
 
+module ROM32K(output[15:0] out, input[14:0] address);
+    reg[15:0] m[0:2**15-1];
+    assign out = m[address];
+endmodule  // ROM32K.
+
 module Computer(input clk, reset);
     wire[15:0] inM, outM, I;
     wire[14:0] addressM, pc;

src/verilog/README.md

@@ -4,7 +4,6 @@ Here are some shortcut to test the chip component.
 
 * [Compile & Test](#compile--test)
 * [ALU (16-bit)](#alu-16-bit)
-* [PC (Program Counter)](#pc-program-counter)
 * [CPU (Central Processing Unit)](#cpu-central-processing-unit)
 * [Memory](#memory)
 * [ROM32K](#rom32k)
@@ -38,17 +37,6 @@ gtkwave tb_alu.vcd
 ```
 
 
-### PC (Program Counter)
-> Reference from [cccbook](https://github.com/cccbook/co/tree/master/code/verilog/nand2tetris),
-  [chipverify.com](https://www.chipverify.com/verilog/verilog-if-else-if)
-
-```
-iverilog -o tb_PC.vvp tb_PC.v
-vvp tb_PC.vvp
-gtkwave tb_PC.vcd
-```
-
-
 ### CPU (Central Processing Unit)
 > Reference from [cccbook](https://github.com/cccbook/co/blob/1c86da267d19d5e2ec1b5e2dfcb6f53cac2cf74e/code/verilog/nand2tetris/computer.v#L18)