在gearbox_64b_66b里面对串行输入打了一拍，保证时序没有问题 #11

developfpga · Mar 19, 2019 · 079fec6 · 079fec6
1 parent dea8492
commit 079fec6
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Showing 3 changed files with 19 additions and 7 deletions.
diff --git a/gth_no_buffer_no_gearbox/rtl/gearbox_64b_66b.v b/gth_no_buffer_no_gearbox/rtl/gearbox_64b_66b.v
@@ -49,6 +49,7 @@ module gearbox_64b_66b (
   reg             r_slip;
   // reg             r_slip_d1;
   // reg             r_slip_d2;
+  reg     [31:0]  r_data;
   reg     [95:0]  r_storage;
   wire    [95:0]  s_aligned_data_in;
   // reg     [30:0]  r_possible_align_bit;
@@ -93,6 +94,14 @@ module gearbox_64b_66b (
   //   end
   // end
 
+  always @(posedge clk_i) begin
+    if(rst_i) begin
+      r_data    <= 'b0;
+    end else begin
+      r_data    <= data_i;
+    end
+  end
+
   always @(posedge clk_i) begin
     if(rst_i) begin
       r_slip    <= 1'b0;
@@ -104,7 +113,7 @@ module gearbox_64b_66b (
       // r_slip_d2 <= r_slip_d1;
     end
   end
-  assign  s_aligned_data_in = ({64'h0, data_i} << r_sft_count2[5:0]);
+  assign  s_aligned_data_in = ({64'h0, r_data} << r_sft_count2[5:0]);
   // assign  s_aligned_data_in = r_sft_count2[6] ? (data_i) : ({64'h0, data_i} << r_sft_count2[5:0]);
 
   always @(posedge clk_i) begin

diff --git a/gtx/rtl/prbs_check.v b/gtx/rtl/prbs_check.v
@@ -12,7 +12,8 @@ module prbs_check (
   input       [1:0]       rx_vldb_i,
   input                   rx_valid_i,
   input                   rx_last_i,
-  input       [0:0]       rx_user_i
+  input       [0:0]       rx_user_i,
+  output                  err_o
 );
 
   reg     [7:0]   r_count;
@@ -22,6 +23,7 @@ module prbs_check (
   reg     [7:0]   r_err2_cnt;
   reg     [7:0]   r_err3_cnt;
 
+  assign  err_o = (|r_err1_cnt) | (|r_err2_cnt) | (|r_err3_cnt);
   always @(posedge rx_user_clk_i) begin
     if(rx_user_rst_i) begin
       r_count   <= 'd0;

diff --git a/gtx/rtl/prbs_test.v b/gtx/rtl/prbs_test.v
@@ -14,7 +14,7 @@ module prbs_test (
   input             gthrxp_i,
   output            gthtxn_o,
   output            gthtxp_o,
-  
+
   // User-provided ports for reset helper block(s)
   input             free_clk_i,
   input             rst_i,
@@ -26,7 +26,7 @@ module prbs_test (
   // parameter                 P_XGMII_LOOPBACK = 1'b0;
   parameter                 P_SCRAMBLE_LOOPBACK = 1'b0;
   parameter                 P_GEARBOX_LOOPBACK = 1'b0;
-  
+
     // AXIS tx
     wire                s_tx_user_clk;
     wire                s_tx_user_rst;
@@ -51,7 +51,7 @@ module prbs_test (
   pcs_top #(
     .P_SCRAMBLE_LOOPBACK    (P_SCRAMBLE_LOOPBACK),
     .P_GEARBOX_LOOPBACK     (P_GEARBOX_LOOPBACK)
-  )u_pcs_top 
+  )u_pcs_top
   (
     .refclk_n_i                       (refclk_n_i),
     .refclk_p_i                       (refclk_p_i),
@@ -60,7 +60,7 @@ module prbs_test (
     .gthrxp_i                         (gthrxp_i),
     .gthtxn_o                         (gthtxn_o),
     .gthtxp_o                         (gthtxp_o),
-    
+
     // User-provided ports for reset helper block(s)
     .hb_gtwiz_reset_clk_freerun_in    (free_clk_i),
     .hb_gtwiz_reset_all_in            (rst_i),
@@ -106,7 +106,8 @@ module prbs_test (
     .rx_vldb_i        (s_rx_vldb),
     .rx_valid_i       (s_rx_valid),
     .rx_last_i        (s_rx_last),
-    .rx_user_i        (s_rx_user)
+    .rx_user_i        (s_rx_user),
+    .err_o            (debug_o)
   );