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增加prbs仿真，处理掉两个bug：
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1、axis2xgmii32.v里面由于输出数据需要每66个时钟暂停2个时钟，所以在读入数据的时候要提前控制一下；
2、xgmii2axis32.v里面也是处理~xgmii_valid时，导致last信号无法有效输出。(DATA,CRC,IDLE,IDLE,T)这种情况last信号输出有问题。
IDLE指xgmii非valid #6
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@developfpga
developfpga committed Mar 18, 2019
1 parent c294345 commit dea8492
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Showing 7 changed files with 496 additions and 207 deletions.
66 changes: 45 additions & 21 deletions gth_no_buffer_with_gearbox/rtl/axis2xgmii32.v
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ module axis2xgmii32 (
******************************************************************************/
reg [6:0] r_66count;
reg r_66b64b_ready;
reg r_start_ready;

reg [P_STATE_WIDTH-1:0] r_state = P_IDLE;
reg r_state_ready;
Expand Down Expand Up @@ -92,6 +93,7 @@ module axis2xgmii32 (
r_sequence_d2 <= 'd0;
r_sequence_d3 <= 'd0;
r_66b64b_ready <= 1'b0;
r_start_ready <= 1'b0;
end else begin
if(r_66count == 65) begin
r_66count <= 'd0;
Expand All @@ -107,6 +109,11 @@ module axis2xgmii32 (
end else begin
r_66b64b_ready <= 1'b1;
end
if(r_66count >= 62 && r_66count <= 63) begin
r_start_ready <= 1'b0;
end else begin
r_start_ready <= 1'b1;
end
end
end
assign s_ready = r_66b64b_ready & r_state_ready;
Expand All @@ -115,55 +122,67 @@ module axis2xgmii32 (
if(rst_i) begin
r_state <= P_IDLE;
end else begin
if(r_66b64b_ready) begin
// if(r_66b64b_ready) begin
case(r_state)
P_IDLE : begin
if(tvalid_i & r_state_ready & ~tlast_i) begin
if(tvalid_i & ~tlast_i & r_state_ready & r_start_ready) begin
r_state <= P_START;
end
end
P_START : begin
// if(tvalid_i == 1'b1) begin
if(r_start_ready == 1'b1) begin
if(tlast_i == 1) begin
r_state <= P_PADDING;
end else begin
r_state <= P_DATA;
end
// end
end
end
P_DATA : begin
if(tlast_i == 1) begin
if(r_input_count >= 56) begin
r_state <= P_END;
end else begin
r_state <= P_PADDING;
if(r_66b64b_ready) begin
if(tlast_i == 1) begin
if(r_input_count >= 56) begin
r_state <= P_END;
end else begin
r_state <= P_PADDING;
end
end
end
end
P_PADDING : begin
if(r_input_count >= 56) begin
r_state <= P_CRC;
if(r_66b64b_ready) begin
if(r_input_count >= 56) begin
r_state <= P_CRC;
end
end
end
P_END : begin
r_state <= P_CRC;
if(r_66b64b_ready) begin
r_state <= P_CRC;
end
end
P_CRC : begin
r_state <= P_CRC_1;
if(r_66b64b_ready) begin
r_state <= P_CRC_1;
end
end
P_CRC_1 : begin
r_state <= P_IPG;
if(r_66b64b_ready) begin
r_state <= P_IPG;
end
end
P_IPG : begin
if(r_ipg_count == P_IPG_COUNT-1) begin
r_state <= P_IDLE;
if(r_66b64b_ready) begin
if(r_ipg_count == P_IPG_COUNT-1) begin
r_state <= P_IDLE;
end
end
end
default : begin
r_state <= P_IDLE;
end
endcase
end
// end
end
end

Expand All @@ -174,7 +193,11 @@ module axis2xgmii32 (
if(r_state == P_IDLE && tvalid_i && s_ready && ~tlast_i) begin
r_input_count <= 'd4;
end else if(r_state == P_START || r_state == P_DATA || r_state == P_PADDING) begin
r_input_count <= r_input_count + 'd4;
if(tvalid_i && s_ready) begin
if(r_input_count < 56) begin
r_input_count <= r_input_count + 'd4;
end
end
end else begin
r_input_count <= 'd0;
end
Expand Down Expand Up @@ -292,7 +315,7 @@ module axis2xgmii32 (
end else begin
case(r_state)
P_IDLE : begin
if(tvalid_i & r_state_ready & ~tlast_i) begin
if(tvalid_i & r_state_ready & r_start_ready & ~tlast_i) begin
r_d <= PREAMBLE_LANE0_D[31:0];
r_c <= PREAMBLE_LANE0_C[3:0];
end else begin
Expand Down Expand Up @@ -333,7 +356,7 @@ module axis2xgmii32 (
2'd2 : begin r_d <= {T,s_crc_final[23:0]}; r_c <= 4'b1000; end
default : begin r_d <= {s_crc_final[31:0]}; r_c <= 4'b0000; end
endcase
r_state <= P_IPG;
// r_state <= P_IPG;
end
P_IPG : begin
r_c <= 4'hf;
Expand All @@ -344,7 +367,8 @@ module axis2xgmii32 (
end
end
default : begin
r_state <= P_IDLE;
r_d <= {4{I}};
r_c <= 4'hf;
end
endcase
end
Expand Down
28 changes: 16 additions & 12 deletions gth_no_buffer_with_gearbox/rtl/xgmii2axis32.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ module xgmii2axis32 (
reg r_tlast_d1;
reg [0:0] r_tuser_d1;

wire s_first_byte_tchar;
reg [31:0] r_tdata_d2;
reg [1:0] r_tvldb_d2;
reg r_tvalid_d2;
Expand Down Expand Up @@ -126,6 +127,7 @@ module xgmii2axis32 (
end // not rst_i
end //always

assign s_first_byte_tchar = (s_c == 4'b1111) && (is_tchar(s_d[7:0]));
always @(posedge clk_i) begin
if(rst_i) begin
r_good_frames <= 'b0;
Expand Down Expand Up @@ -244,12 +246,12 @@ module xgmii2axis32 (
r_tuser_d1 <= 'd0;
end
endcase
end else begin
r_tdata_d1 <= 'd0;
r_tvldb_d1 <= 'd0;
r_tvalid_d1 <= 'd0;
r_tlast_d1 <= 'd0;
r_tuser_d1 <= 'd0;
// end else begin
// r_tdata_d1 <= 'd0;
// r_tvldb_d1 <= 'd0;
// r_tvalid_d1 <= 'd0;
// r_tlast_d1 <= 'd0;
// r_tuser_d1 <= 'd0;
end
end
end
Expand All @@ -261,9 +263,11 @@ module xgmii2axis32 (
r_tvldb_d2 <= 'd0;
r_tvalid_d2 <= 'd0;
end else begin // not rst_i
r_tdata_d2 <= r_tdata_d1;
r_tvldb_d2 <= r_tvldb_d1;
if(r_tlast_d1 & r_tvalid_d1) begin
if(s_xgmii_valid) begin
r_tdata_d2 <= r_tdata_d1;
r_tvldb_d2 <= r_tvldb_d1;
end
if((r_tlast_d1 & r_tvalid_d1) | (s_first_byte_tchar)) begin
r_tvalid_d2 <= 1'b0;
end else begin
r_tvalid_d2 <= r_tvalid_d1;
Expand Down Expand Up @@ -291,7 +295,7 @@ module xgmii2axis32 (
end
end
end

assign s_crc_32_4b = ~crc_rev(r_crc_32);
assign s_crc_32_3b = ~crc_rev(r_crc_32_3b);
assign s_crc_32_2b = ~crc_rev(r_crc_32_2b);
Expand All @@ -304,7 +308,7 @@ module xgmii2axis32 (

assign tdata_o = r_tdata_d2;
assign tvldb_o = r_tvldb_d2;
assign tvalid_o = r_tvalid_d2;
assign tlast_o = r_tlast_d1;
assign tvalid_o = r_tvalid_d2 & s_xgmii_valid;
assign tlast_o = r_tlast_d1 | s_first_byte_tchar;
assign tuser_o = r_tuser_d1;
endmodule // xgmii2axis32
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