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[Intel-SIG] Intel 14th MTL graphics sync from 6.7 to 6.10-rc1 #327

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efeda1f
drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
guludo Aug 14, 2023
2f6ed50
drm/i915: Simplify intel_cx0_program_phy_lane() with loop
guludo Aug 14, 2023
b18a16c
drm/i915/cx0: Program vswing only for owned lanes
guludo Aug 14, 2023
2cdfe15
drm/i915/dp_mst: Use output_format to get the final link bpp
aknautiyal Aug 17, 2023
9767bc0
drm/i915/regs: split out intel_color_regs.h
jnikula Aug 17, 2023
2fec774
drm/i915/color: move CHV CGM pipe mode read to intel_color
jnikula Aug 17, 2023
7b5e355
drm/i915: move HSW+ gamma mode read to intel_color
jnikula Aug 17, 2023
8df6d43
drm/i915: move ILK+ CSC mode read to intel_color
jnikula Aug 17, 2023
69a5a6d
drm/i915/color: move SKL+ gamma and CSC enable read to intel_color
jnikula Aug 17, 2023
dc54579
drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color
jnikula Aug 17, 2023
d58ccef
drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim
surajk8 Aug 28, 2023
c650fd5
drm/i915: add minimal i915_gem_object_frontbuffer.h
jnikula Aug 30, 2023
c9e341a
drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid
jnikula Aug 25, 2023
19c731a
drm/edid: add drm_edid_is_digital()
jnikula Aug 24, 2023
6a577d8
drm/edid: parse source physical address
jnikula Aug 24, 2023
50f0d1b
drm/i915/display: use drm_edid_is_digital()
jnikula Aug 24, 2023
3598121
drm/i915/hdcp: Use intel_connector as argument for hdcp_2_2_capable
surajk8 Aug 30, 2023
15b5da2
drm/i915/dsb: Dump the DSB command buffer when DSB fails
vsyrjala Jun 6, 2023
c728051
drm/i915/dsb: Avoid corrupting the first register write
vsyrjala Jun 6, 2023
872bb68
drm/i915/dsb: Don't use indexed writes when byte enables are not all set
vsyrjala Jun 6, 2023
e9da49b
drm/i915: Call the DDC bus i2c adapter "ddc"
vsyrjala Aug 31, 2023
3594f05
drm/i915/hdmi: Use connector->ddc everwhere
vsyrjala Aug 29, 2023
d3d16b8
drm/i915/hdmi: Nuke hdmi->ddc_bus
vsyrjala Aug 29, 2023
9f92ff6
drm/i915/hdmi: Remove old i2c symlink
vsyrjala Aug 29, 2023
53a04c0
drm/i915: move more of the display probe to display code
jnikula Sep 12, 2023
0484625
drm/i915: Move psr unlock out from the pipe update critical section
vsyrjala Sep 1, 2023
ef6629d
drm/i915: Optimize out redundant M/N updates
vsyrjala Sep 1, 2023
6b36083
drm/i915: Relocate is_in_vrr_range()
vsyrjala Sep 1, 2023
ffbe24b
drm/i915: Validate that the timings are within the VRR range
vsyrjala Sep 1, 2023
907235e
drm/i915: Disable VRR during seamless M/N changes
vsyrjala Sep 1, 2023
92b09c4
drm/i915: Update VRR parameters in fastset
vsyrjala Sep 1, 2023
dc04adb
drm/i915: Assert that VRR is off during vblank evasion if necessary
vsyrjala Sep 1, 2023
0c41f1f
drm/i915: Implement transcoder LRR for TGL+
vsyrjala Sep 15, 2023
d679222
drm/i915: Re-order if/else ladder in intel_detect_pch()
lucasdemarchi Sep 19, 2023
8a5446c
drm/i915/xe2lpd: Add fake PCH
guludo Sep 19, 2023
3989147
drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
StanFox1984 Sep 19, 2023
3ebf0bc
drm/i915/xe2lpd: Read pin assignment from IOM
lucacoelho Sep 19, 2023
2c35ee7
drm/i915/lnl: Add gmbus/ddc support
lucasdemarchi Sep 19, 2023
cec39b5
drm/i915/xe2lpd: Add support for HPD
guludo Sep 19, 2023
a00cfa5
drm/i915/dsb: Use non-locked register access
vsyrjala Jun 6, 2023
413e5b4
drm/i915/dsb: Define more DSB bits
vsyrjala Jun 6, 2023
91164b9
drm/i915/dsb: Define the contents of some intstructions bit better
vsyrjala Jun 6, 2023
54062e8
drm/i915/dsb: Introduce intel_dsb_noop()
vsyrjala Jun 6, 2023
6a66ecc
drm/i915/dsb: Introduce intel_dsb_reg_write_masked()
vsyrjala Jun 6, 2023
5b1d43e
drm/i915/dsb: Add support for non-posted DSB registers writes
vsyrjala Jun 6, 2023
e60737f
drm/i915/dsb: Load LUTs using the DSB during vblank
vsyrjala Jun 6, 2023
09cf74a
drm/i915/dsb: Evade transcoder undelayed vblank when using DSB
vsyrjala Jun 6, 2023
8164620
drm/i915: Introduce skl_watermark_max_latency()
vsyrjala Jun 6, 2023
1815f8d
drm/i915: Introduce intel_crtc_scanline_to_hw()
vsyrjala Jun 6, 2023
5ab028d
drm/i915/dsb: Use DEwake to combat PkgC latency
vsyrjala Jun 6, 2023
9bc181a
drm/i915: Add helper to modeset a set of pipes
ideak Sep 21, 2023
9f3f682
drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes…
ideak Sep 21, 2023
6e41343
drm/i915: Factor out a helper to check/compute all the CRTC states
ideak Sep 21, 2023
a22fc97
drm/i915/mocs: use to_gt() instead of direct &i915->gt
jnikula Oct 2, 2023
10a246b
drm/i915: Constify the snps/c10x PLL state checkers
vsyrjala Oct 4, 2023
2b40ab2
drm/i915/dsb: Allocate command buffer from local memory
vsyrjala Oct 9, 2023
6b750a6
drm/i915/dsb: Correct DSB command buffer cache coherency settings
vsyrjala Oct 9, 2023
911daf7
drm/i915/display: Reset message bus after each read/write operation
mkahola Oct 16, 2023
8091210
drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code
vsyrjala Oct 12, 2023
0fd0e94
drm/i915/dsb: DSB code refactoring
animesh-manna Nov 10, 2023
7e8b152
drm/i915: move *_crtc_clock_get() to intel_dpll.c
jnikula Nov 14, 2023
bc11394
drm/i915/psr: Move plane sel fetch configuration into plane source files
hogander Nov 20, 2023
044d0f9
drm/i915/dgfx: DGFX uses direct VBT pin mapping
cataylox Nov 28, 2023
347011d
drm/i915: correct the input parameter on _intel_dsb_commit()
Nov 14, 2023
8403e75
drm/i915: Stop accessing crtc->state from the flip done irq
vsyrjala Sep 28, 2023
f37b57d
drm/i915/display: Take care of VSC select field in video dip ctl regi…
hogander Dec 20, 2023
28b814b
drm/i915/mtl: Add fake PCH for Meteor Lake
hkalvala Dec 19, 2023
334ac92
drm/i915: Disable DSB in Xe KMD
zehortigoza Jan 4, 2024
468e6ef
drm/i915: Add additional ARL PCI IDs
mattrope Jan 8, 2024
111a4fe
drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+
harishchegondi Jan 8, 2024
c8bf9f2
drm/i915: Decouple intel_crtc_vblank_evade_scanlines() from atomic co…
vsyrjala Dec 13, 2023
0bfd595
drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa
vsyrjala Dec 13, 2023
aa83a06
drm/i915: Introduce struct intel_vblank_evade_ctx
vsyrjala Dec 13, 2023
38bdf03
drm/i915: Include need_vlv_dsi_wa in intel_vblank_evade_ctx
vsyrjala Dec 13, 2023
4009360
drm/i915: Extract intel_vblank_evade()
vsyrjala Dec 13, 2023
35880aa
drm/i915: Move the min/max scanline sanity check into intel_vblank_ev…
vsyrjala Dec 13, 2023
2822aae
drm/i915: Perform vblank evasion around legacy cursor updates
vsyrjala Jan 16, 2024
62a4079
Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB …
vsyrjala Dec 13, 2023
06d2114
drm/i915/mtl: Wake GT before sending H2G message
vsbelgaum Jan 19, 2024
43f1429
drm/i915/xe2lpd: Move D2D enable/disable
lucasdemarchi Jan 26, 2024
5691853
drm/print: move enum drm_debug_category etc. earlier in drm_print.h
jnikula Jan 16, 2024
b23e145
drm/i915: Move intel_vblank_evade() & co. into intel_vblank.c
vsyrjala Dec 13, 2023
44dae7f
drm/i915/display: update pll values in sync with Bspec for MTL
vodapalliravi12 Feb 14, 2024
e208700
drm/i915/lnl: Add pkgc related register
surajk8 Feb 1, 2024
e70d9f7
drm/i915/vrr: Generate VRR "safe window" for DSB
vsyrjala Mar 6, 2024
5b75fcb
drm/i915/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
jnikula Mar 20, 2024
9f37158
drm/i915/dp: Remove support for UHBR13.5
armurthy Feb 28, 2024
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Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB …
…allocation"

commit 6bc41f9 upstream.

This reverts commit cfeff35.

A core design consideration with legacy cursor updates is that the
cursor must not touch any other plane, even if we were to force it
to take the slow path. That is the real reason why the cursor uses
a fixed ddb allocation, not because bspec says so.

Treating cursors as any other plane during ddb allocation
violates that, which means we can now pull other planes into
fully unsynced legacy cursor mailbox commits. That is
definitely not something we've ever considered when designing
the rest of the code. The noarm+arm register write split in
particular makes that dangerous as previous updates can get
disarmed pretty much at any random time, and not necessarily
in an order that is actually safe (eg. against ddb overlaps).

So if we were to do this then:
- someone needs to expend the appropriate amount of brain
  cells thinking through all the tricky details
- we should do it for all skl+ platforms since all
  of those have double buffered wm/ddb registers. The current
  arbitrary mtl+ cutoff doesn't really make sense

For the moment just go back to the original behaviour where
the cursor's ddb alloation does not change outside of
modeset/fastset. As of now anything else isn't safe.

deepin-Intel-SIG: commit 6bc41f9 Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation".
MTL Graphics backporting - 2024Q2

Cc: Stanislav Lisovskiy <[email protected]>
Cc: Matt Roper <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Stanislav Lisovskiy <[email protected]>
Reviewed-by: Uma Shankar <[email protected]>
[ Quanxian Wang: amend commit log ]
Signed-off-by: Quanxian Wang <[email protected]>
vsyrjala authored and quanxianwang committed Jul 19, 2024

Verified

This commit was signed with the committer’s verified signature.
caixw caixw
commit 62a40792c6780f62e0ff378cbdd0e064cb3735a3
6 changes: 3 additions & 3 deletions drivers/gpu/drm/i915/display/intel_atomic_plane.c
Original file line number Diff line number Diff line change
@@ -214,6 +214,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
int width, height;
unsigned int rel_data_rate;

if (plane->id == PLANE_CURSOR)
return 0;

if (!plane_state->uapi.visible)
return 0;

@@ -241,9 +244,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,

rel_data_rate = width * height * fb->format->cpp[color_plane];

if (plane->id == PLANE_CURSOR)
return rel_data_rate;

return intel_adjusted_rate(&plane_state->uapi.src,
&plane_state->uapi.dst,
rel_data_rate);
16 changes: 7 additions & 9 deletions drivers/gpu/drm/i915/display/skl_watermark.c
Original file line number Diff line number Diff line change
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
u64 data_rate = 0;

for_each_plane_id_on_crtc(crtc, plane_id) {
if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
if (plane_id == PLANE_CURSOR)
continue;

data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,12 +1514,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
return 0;

/* Allocate fixed number of blocks for cursor. */
if (DISPLAY_VER(i915) < 20) {
cursor_size = skl_cursor_allocation(crtc_state, num_active);
iter.size -= cursor_size;
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
alloc->end - cursor_size, alloc->end);
}
cursor_size = skl_cursor_allocation(crtc_state, num_active);
iter.size -= cursor_size;
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
alloc->end - cursor_size, alloc->end);

iter.data_rate = skl_total_relative_data_rate(crtc_state);

@@ -1533,7 +1531,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];

if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
if (plane_id == PLANE_CURSOR) {
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];

@@ -1581,7 +1579,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];

if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
if (plane_id == PLANE_CURSOR)
continue;

if (DISPLAY_VER(i915) < 11 &&