[Intel-SIG] Intel 14th MTL graphics sync from 6.7 to 6.10-rc1 #327
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
commit 3a8ecd4 upstream. There are more parts of C10/C20 programming that need to take owned lanes into account. Define the function intel_cx0_get_owned_lane_mask() and use it. There will be new users of that function in upcoming changes. BSpec: 64539 deepin-Intel-SIG: commit 3a8ecd4 drm/i915/cx0: Add intel_cx0_get_owned_lane_mask(). MTL Graphics backporting - 2024Q2 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 0f5c2e5 upstream. It is possible to generalize the "disable" value for the transmitters to be a bit mask based on the port width and the port reversal boolean, with a small exception for DP-alt mode with "x1" port width. Simplify the code by using such a mask and a for-loop instead of using switch-case statements. v2: - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection. (Jani) BSpec: 64539 deepin-Intel-SIG: commit 0f5c2e5 drm/i915: Simplify intel_cx0_program_phy_lane() with loop. MTL Graphics backporting - 2024Q2 Cc: Jani Nikula <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 226fa3a upstream. According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY lane. BSpec: 74103, 74104 deepin-Intel-SIG: commit 226fa3a drm/i915/cx0: Program vswing only for owned lanes. MTL Graphics backporting - 2024Q2 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit fd279d2 upstream. The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. deepin-Intel-SIG: commit fd279d2 drm/i915/dp_mst: Use output_format to get the final link bpp. MTL Graphics backporting - 2024Q2 Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit ae3a70a upstream. Declutter i915_regs.h. deepin-Intel-SIG: commit ae3a70a drm/i915/regs: split out intel_color_regs.h. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8e76007a361bd3ca8dd8913281854886b3a1954c.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 7f52ca6 upstream. Add color .get_config hook to read config other than LUTs and CSCs, and start off with CHV CGM pipe mode to abstract the platform specific register access better. deepin-Intel-SIG: commit 7f52ca6 drm/i915/color: move CHV CGM pipe mode read to intel_color. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1444200931ae61b6360e3dcad8cbea206ad62e2f.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit efe6fcb upstream. Abstract the platform specific register access better. The separate hsw_read_gamma_mode() will make more sense with the following changes. deepin-Intel-SIG: commit efe6fcb drm/i915: move HSW+ gamma mode read to intel_color. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/b7ddcc8b0fb783eb149864070821bdb695c40366.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit cecdea1 upstream. Abstract the platform specific register access better. deepin-Intel-SIG: commit cecdea1 drm/i915: move ILK+ CSC mode read to intel_color. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8f34c577c663839020405e96cdb464319c2881d4.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit f56e23e upstream. Abstract the platform specific register access better. deepin-Intel-SIG: commit f56e23e drm/i915/color: move SKL+ gamma and CSC enable read to intel_color. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c0c37c06d1f2673c82d567c8bcbb6b0b0054b5fa.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 9af09df upstream. Abstract the register access better. The DSPCNTR read could be moved to either i9xx_plane.c or intel_color.c. The latter feels better, even if the register is written in the former. deepin-Intel-SIG: commit 9af09df drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/33830dba5d69027469d976f6909740ccff8c7281.1692287501.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 51152ac upstream. Update intel_hdcp_shim funcs specifically read_2_2_message, write_2_2_message and config_stream_type to use intel_connector argument instead of intel_digital_port as this will help in getting correct aux later for dp mst scenarios also already hdcp funcs derive digital_port from connector and then many funcs again get back the connector from dig_port which doesn't seem right. Connector specific hdcp functions can derive dig_port on need basis. deepin-Intel-SIG: commit 51152ac drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim. MTL Graphics backporting - 2024Q2 Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit c1464a8 upstream. Split out frontbuffer related declarations and static inlines from gem/i915_gem_object.h into new gem/i915_gem_object_frontbuffer.h. The main goal is to reduce header interdependencies. With gem/i915_gem_object.h including display/intel_frontbuffer.h, modification of the latter causes a whopping 300+ objects to be rebuilt, while many of the source files actually needing it aren't explicitly including it at all. After the change, only 21 objects depend on display/intel_frontbuffer.h, directly or indirectly. deepin-Intel-SIG: commit c1464a8 drm/i915: add minimal i915_gem_object_frontbuffer.h. MTL Graphics backporting - 2024Q2 Cc: Jouni Högander <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 113cddd upstream. Connectors have source physical address available in display info. There's no need to parse the EDID again for this. Add drm_dp_cec_attach() to do this. Seems like the set_edid/unset_edid naming is a bit specific now that there's no need to pass the EDID at all, so aim for attach/detach going forward. v2: Fix the embarrashing build failures deepin-Intel-SIG: commit 113cddd drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid. MTL Graphics backporting - 2024Q2 Cc: Hans Verkuil <[email protected]> Cc: [email protected] Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Hans Verkuil <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 7218779 upstream. Checking edid->input & DRM_EDID_INPUT_DIGITAL is common enough to deserve a helper that also lets us abstract the raw EDID a bit better. deepin-Intel-SIG: commit 7218779 drm/edid: add drm_edid_is_digital(). MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/4bdb407bf189fd922be022eb2f9564692377c81d.1692884619.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 82b599e upstream. CEC needs the source physical address. Parsing it is trivial with the existing EDID CEA DB infrastructure. Default to CEC_PHYS_ADDR_INVALID (0xffff) instead of 0 to cater for easier CEC usage. deepin-Intel-SIG: commit 82b599e drm/edid: parse source physical address. MTL Graphics backporting - 2024Q2 Cc: Hans Verkuil <[email protected]> Cc: [email protected] Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Hans Verkuil <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8c6b6403932536b6849e0b44e1ee6e7ebdbe4a69.1692884619.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit e1039cd upstream. Reduce the use of struct edid and drm_edid_raw(). deepin-Intel-SIG: commit e1039cd drm/i915/display: use drm_edid_is_digital(). MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/dbc0269d34f3140aff410eefae8a2711c59299b3.1692884619.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 130849f upstream. Use intel_connector as argument instead of intel_digital_port in hdcp_2_2_capable function and dig_port can be later derived from connector. This will help with getting the correct hdcp version of particular monitor in a MST setup. deepin-Intel-SIG: commit 130849f drm/i915/hdcp: Use intel_connector as argument for hdcp_2_2_capable. MTL Graphics backporting - 2024Q2 Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 9055e73 upstream. Dump the full DSB command buffers and head/tail pointers if the the DSB hasn't completed its job in time. deepin-Intel-SIG: commit 9055e73 drm/i915/dsb: Dump the DSB command buffer when DSB fails. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Animesh Manna <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 088ca02 upstream. i915_gem_object_create_internal() does not hand out zeroed memory. Thus we may confuse whatever stale garbage is in there as a previous register write and mistakenly handle the first actual register write as an indexed write. This can end up corrupting the instruction sufficiently well to lose the entire register write. Make sure we've actually emitted a previous instruction before attemting indexed register write merging. deepin-Intel-SIG: commit 088ca02 drm/i915/dsb: Avoid corrupting the first register write. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Animesh Manna <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 231b1d6 upstream. The indexed write instruction doesn't support byte-enables, so if the non-indexed write used those we must not convert it to an indexed write. deepin-Intel-SIG: commit 231b1d6 drm/i915/dsb: Don't use indexed writes when byte enables are not all set. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Animesh Manna <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 30b98ec upstream. Rename the various names we've used for the DDC bus i2c adapter ("i2c", "adapter", etc.) to just "ddc". This differentiates it from the various other i2c busses we might have (DSI panel stuff, DVO control bus, etc.). v2: Don't add a bogus drm_get_edid() call (Jani) deepin-Intel-SIG: commit 30b98ec drm/i915: Call the DDC bus i2c adapter "ddc". MTL Graphics backporting - 2024Q2 Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit e046d15 upstream. We already populate connector->ddc for HDMI ports, but so far we've not taken full advantage of it. Do that by eliminating a bunch of intel_gmbus_get_adapter() lookups. deepin-Intel-SIG: commit e046d15 drm/i915/hdmi: Use connector->ddc everwhere. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit ac6dcb6 upstream. Remove the mostly redundant hdmi->ddc_bus. The only thing that needs it anymore is get_encoder_by_ddc_bus(), but that can be replaced with a slight detour through attached_connector+intel_gmbus_get_adapter(). deepin-Intel-SIG: commit ac6dcb6 drm/i915/hdmi: Nuke hdmi->ddc_bus. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 31a6575 upstream. Remove the i915 specific i2c-N symlink from HDMI connectors. This was added to sort of mirror the DP connectors that alreayd had their aux ch based i2c adapter sitting beneath them in the sysfs hierarchy. But now that we have the standard "ddc" symlink approach provided by the core let's switch to that fully. I don't think anything beyond igt depends on this. deepin-Intel-SIG: commit 31a6575 drm/i915/hdmi: Remove old i2c symlink. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6686c30 upstream. Initializing i915->display.info.__device_info and DISPLAY_RUNTIME_INFO() really belongs in display code. Move them there. deepin-Intel-SIG: commit 6686c30 drm/i915: move more of the display probe to display code. MTL Graphics backporting - 2024Q2 Cc: Matt Roper <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit f895e3d upstream. Do the PSR unlock after the vblank evade critcal section is fully over, not before. deepin-Intel-SIG: commit f895e3d drm/i915: Move psr unlock out from the pipe update critical section. MTL Graphics backporting - 2024Q2 Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit b4ac591 upstream. Don't perform a seamless M/N update if the values aren't actually changing. This avoids doing extra shenanigans during vblank evasion needlessly. deepin-Intel-SIG: commit b4ac591 drm/i915: Optimize out redundant M/N updates. MTL Graphics backporting - 2024Q2 Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit f0f7ec7 upstream. Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and rename it accordingly. deepin-Intel-SIG: commit f0f7ec7 drm/i915: Relocate is_in_vrr_range(). MTL Graphics backporting - 2024Q2 Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6a38b36 upstream. Let's assume there are some crazy displays where the high end of the VRR range ends up being lower than the refresh rate as determined by the actual timings. In that case when we toggle VRR on/off we would step outside the VRR range when toggling VRR on/off. Let's just make sure that never happens by not using VRR in such cases. If the user really wants VRR they should then select the timings to land within the VRR range. deepin-Intel-SIG: commit 6a38b36 drm/i915: Validate that the timings are within the VRR range. MTL Graphics backporting - 2024Q2 Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 8f78227 upstream. Make life less confusing by making sure VRR is disabled whenever we do any drastic changes to the display timings, such as seamless M/N changes. deepin-Intel-SIG: commit 8f78227 drm/i915: Disable VRR during seamless M/N changes. MTL Graphics backporting - 2024Q2 Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 98ed369 upstream. Refactor DSB implementation to be compatible with Xe driver. v1: RFC version. v2: Make intel_dsb structure opaque from external usage. [Jani] v3: Rebased on latest. v4: - Add boundary check in dsb_buffer_memset(). [Luca] - Use size_t instead of u32. [Luca] v5: WARN_ON() added for out of boudary case with some optimization. [Luca] v6: Rebased on latest and fix a rebase-miss. deepin-Intel-SIG: commit 98ed369 drm/i915/dsb: DSB code refactoring. MTL Graphics backporting - 2024Q2 Cc: Jani Nikula <[email protected]> Reviewed-by: Luca Coelho <[email protected]> Signed-off-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 9d69533 upstream. Considering what the functions do, intel_dpll.c is a more suitable location, and lets us make some functions static while at it. This also means intel_display.c no longer does any DPIO access. deepin-Intel-SIG: commit 9d69533 drm/i915: move *_crtc_clock_get() to intel_dpll.c. MTL Graphics backporting - 2024Q2 Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit b1f5279 upstream. Currently selective fetch configuration for planes is implemented in psr code. More suitable place for this code is where everything else is configured for planes -> move it into skl_universal_plane.c and intel_cursor.c. This also allows us to drop hooks for cursor handling. v3: Checkpatch warnings fixed v2: Removed setting sel_fetch_area->y1/y2 as -1 deepin-Intel-SIG: commit b1f5279 drm/i915/psr: Move plane sel fetch configuration into plane source files. MTL Graphics backporting - 2024Q2 Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 562f338 upstream. DDC pin mapping for DGFX cards uses direct VBT pin mapping deepin-Intel-SIG: commit 562f338 drm/i915/dgfx: DGFX uses direct VBT pin mapping. MTL Graphics backporting - 2024Q2 Cc: Lucas De Marchi <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Clint Taylor <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit ef32c3c upstream. Current, the dewake_scanline variable is defined as unsigned int, an unsigned int variable that is always greater than or equal to 0. when _intel_dsb_commit function is called by intel_dsb_commit function, the dewake_scanline variable may have an int value. So the dewake_scanline variable is necessary to defined as an int. Fixes: f83b94d ("drm/i915/dsb: Use DEwake to combat PkgC latency") Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ deepin-Intel-SIG: commit ef32c3c drm/i915: correct the input parameter on _intel_dsb_commit(). MTL Graphics backporting - 2024Q2 Cc: Ville Syrjälä <[email protected]> Cc: Uma Shankar <[email protected]> Signed-off-by: heminhong <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6128bec upstream. Assuming crtc->state is pointing at the correct thing for the async flip commit is nonsense. If we had already queued up multiple commits this would point at the very lates crtc state even if the older commits hadn't even happened yet. Instead properly stage/arm the event like we do for async flips. Since we don't need to arm multiple of these at the same time we don't need a list like the normal vblank even processing uses. deepin-Intel-SIG: commit 6128bec drm/i915: Stop accessing crtc->state from the flip done irq. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Arun R Murthy <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
…ster commit bac2d7d upstream. We need to configure VSC Select field in video dip ctl if we want to have e.g. colorimetry date in our VSC SDP. deepin-Intel-SIG: commit bac2d7d drm/i915/display: Take care of VSC select field in video dip ctl register. MTL Graphics backporting - 2024Q2 Signed-off-by: Jouni Högander <[email protected]> Acked-by: Rodrigo Vivi <[email protected]> Tested-by: Shawn Lee <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 93cbc1a upstream. Correct the implementation trying to detect MTL PCH with the MTL fake PCH id. On MTL, both the North Display (NDE) and South Display (SDE) functionality reside on the same die (the SoC die in this case), unlike many past platforms where the SDE was on a separate PCH die. The code is (badly) structured today in a way that assumes the SDE is always on the PCH for modern platforms, so on platforms where we don't actually need to identify the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows us to avoid restructuring a bunch of the code.we've been assigning a "fake PCH" as a quick hack that allows us to avoid restructuring a bunch of the code. Removed unused macros of LNL amd MTL as well. v2: Reorder PCH_MTL conditional check (Matt Roper) Reverting to PCH_MTL for PICA interrupt(Matt Roper) deepin-Intel-SIG: commit 93cbc1a drm/i915/mtl: Add fake PCH for Meteor Lake. MTL Graphics backporting - 2024Q2 Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit c27f010 upstream. Often getting DSB overflows when starting Xorg or Wayland compositors when running Xe KMD. Issue was reported but nothing was done, so disabling DSB as whole until properly fixed in Xe KMD. v2: - move check to HAS_DSB(Jani) v3: - use IS_ENABLED(I915) check in intel_dsb_prepare() Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/989 Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1031 Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1072 deepin-Intel-SIG: commit c27f010 drm/i915: Disable DSB in Xe KMD. MTL Graphics backporting - 2024Q2 Cc: Animesh Manna <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Francois Dugast <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit bddacdf upstream. Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list. Bspec: 55420 deepin-Intel-SIG: commit bddacdf drm/i915: Add additional ARL PCI IDs. MTL Graphics backporting - 2024Q2 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 84bf82f upstream. Xe_LPG+ (IP version 12.74) should take the same general code paths as Xe_LPG (versions 12.70 and 12.71). Xe_LPG+'s workaround list will be handled by the next patch. deepin-Intel-SIG: commit 84bf82f drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+. MTL Graphics backporting - 2024Q2 Signed-off-by: Harish Chegondi <[email protected]> Signed-off-by: Haridhar Kalvala <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
…mmits commit c045bc4 upstream. We'll be needing to do vblank evasion around legacy cursor updates, which don't have the intel_atomic_state around. So let's remove this dependency on a full commit and pass the crtc state in by hand. deepin-Intel-SIG: commit c045bc4 drm/i915: Decouple intel_crtc_vblank_evade_scanlines() from atomic commits. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit bb83f34 upstream. Drop the vblank reference only after we've done the hideous need_vlv_dsi_wa stuff. This will make it easier to reuse the the vblank evasion machinery elsewhere. Keeping the vblank reference for a bit longer is not a problem. In fact we might want to not drop it at all until intel_pipe_update_end(), but we'll leave that idea for later. deepin-Intel-SIG: commit bb83f34 drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 637bda5 upstream. Collect the information needed for vblank evasions into a structure that we can pass around more easily. And let's rename intel_crtc_vblank_evade_scanlines() to just intel_vblank_evade_init() so that better describes the intended usage of initializing the context. deepin-Intel-SIG: commit 637bda5 drm/i915: Introduce struct intel_vblank_evade_ctx. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit b1f9bc3 upstream. Pull the need_vlv_dsi_wa details into intel_vblank_evade_init() so that caller doesn't have to care about it. deepin-Intel-SIG: commit b1f9bc3 drm/i915: Include need_vlv_dsi_wa in intel_vblank_evade_ctx. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit b5ad7ce upstream. Pull the core vblank evasion loop into its own function, so that we can reuse it elsewhere later. deepin-Intel-SIG: commit b5ad7ce drm/i915: Extract intel_vblank_evade(). MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
…ade() commit 318ec32 upstream. There isn't really any reason to make the caller suffer through checking the vblank evasion min/max scanlines. If we somehow ended up with bogus values (which really shouldn't happen) then just skip the actual vblank evasion loop but otherwise plow ahead as normal. The only "real" change is that we now get+put a vblank reference even if the min/max values are bogus, previously we skipped directly to the end. deepin-Intel-SIG: commit 318ec32 drm/i915: Move the min/max scanline sanity check into intel_vblank_evade(). MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 1de6352 upstream. Our legacy cursor updates are actually mailbox updates. Ie. the hardware latches things once per frame on start of vblank, but we issue an number of updates per frame, withough any attempt to synchronize against the vblank in software. So in theory only the last update issued during the frame will latch, and the previous ones are discarded. However this can lead to problems with maintaining the ggtt/iommu mappings as we have no idea which updates will actually latch. The problem is exacerbated by the hardware's annoying disarming behaviour; any non-arming register write will disarm an already armed update, only to be rearmed later by the arming register (CURBASE in case of cursors). If a disarming write happens just before the start of vblank, and the arming write happens after start of vblank we have effectively prevented the hardware from latching anything. And if we manage to straddle multiple sequential vblank starts in this manner we effectively prevent the hardware from latching any new registers for an arbitrary amount of time. This provides more time for the (potentially still in use by the hardware) gtt/iommu mappings to be torn down. A partial solution, of course, is to use vblank evasion to avoid the register writes from spreading on both sides of the start of vblank. I've previously highlighted this problem as a general issue affecting mailbox updates. I even added some notes to the {i9xx,skl}_crtc_planes_update_arm() to remind us that the noarm and arm phases both need to pulled into the vblank evasion critical section if we actually decided to implement mailbox updates in general. But as I never impelemented the noarm+arm split for cursors we don't have to worry about that for the moment. We've been lucky enough so far that this hasn't really caused problems. One thing that does help is that Xorg generally sticks to the same cursor BO. But igt seems pretty good at hitting this on MTL now, so apparently we have to start thinking about this. v2: Wait for PSR exit to avoid the vblank evasion timeout (1ms) tripping due to PSR exit latency (~5ms typically) deepin-Intel-SIG: commit 1de6352 drm/i915: Perform vblank evasion around legacy cursor updates. MTL Graphics backporting - 2024Q2 Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jouni Högander <[email protected]> Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
…allocation" commit 6bc41f9 upstream. This reverts commit cfeff35. A core design consideration with legacy cursor updates is that the cursor must not touch any other plane, even if we were to force it to take the slow path. That is the real reason why the cursor uses a fixed ddb allocation, not because bspec says so. Treating cursors as any other plane during ddb allocation violates that, which means we can now pull other planes into fully unsynced legacy cursor mailbox commits. That is definitely not something we've ever considered when designing the rest of the code. The noarm+arm register write split in particular makes that dangerous as previous updates can get disarmed pretty much at any random time, and not necessarily in an order that is actually safe (eg. against ddb overlaps). So if we were to do this then: - someone needs to expend the appropriate amount of brain cells thinking through all the tricky details - we should do it for all skl+ platforms since all of those have double buffered wm/ddb registers. The current arbitrary mtl+ cutoff doesn't really make sense For the moment just go back to the original behaviour where the cursor's ddb alloation does not change outside of modeset/fastset. As of now anything else isn't safe. deepin-Intel-SIG: commit 6bc41f9 Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation". MTL Graphics backporting - 2024Q2 Cc: Stanislav Lisovskiy <[email protected]> Cc: Matt Roper <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]> Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 6d46d09 upstream. Instead of waiting until the interrupt reaches GuC, we can grab a forcewake while triggering the H2G interrupt. GEN11_GUC_HOST_INTERRUPT is inside sgunit and is not affected by forcewakes. However, there could be some delays when platform is entering/exiting some higher level platform sleep states and a H2G is triggered. A forcewake ensures those sleep states have been fully exited and further processing occurs as expected. The hysteresis timers for C6 and higher sleep states will ensure there is no unwanted race between the wake and processing of the interrupts by GuC. This will have an official WA soon so adding a FIXME in the comments. v2: Make the new ranges watertight to address BAT failures and update commit message (Matt R). deepin-Intel-SIG: commit 6d46d09 drm/i915/mtl: Wake GT before sending H2G message. MTL Graphics backporting - 2024Q2 Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Vinay Belgaumkar <[email protected]> Signed-off-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit d5c7854 upstream. Bits to enable/disable and check state for D2D moved from XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec). Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with multiple reg location and bitfield layout. v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_ENABLE in saved_port_bits when enabling/disabling D2D so DDI_BUF_CTL is correctly programmed in other places without overriding these bits (Clint) v3: Leave saved_port_bits alone as those bits are not meant to be modified outside of the port initialization. Rather propagate the additional bit in DDI_BUF_CTL to be set when that register is written again after D2D is enabled. deepin-Intel-SIG: commit d5c7854 drm/i915/xe2lpd: Move D2D enable/disable. MTL Graphics backporting - 2024Q2 Cc: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 82195d4 upstream. Avoid forward declarations in subsequent changes, but separate this movement to an independent change. deepin-Intel-SIG: commit 82195d4 drm/print: move enum drm_debug_category etc. earlier in drm_print.h. MTL Graphics backporting - 2024Q2 Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Luca Coelho <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/9d105014e3c90af13a874745d768212347f68283.1705410327.git.jani.nikula@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit dea1731 upstream. intel_vblank.c seems like the appropriate place for the core vblank evasion code. Move it there. deepin-Intel-SIG: commit dea1731 drm/i915: Move intel_vblank_evade() & co. into intel_vblank.c. MTL Graphics backporting - 2024Q2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit d9b904d upstream. DP/eDP and HDMI C20 PHY PLL values were updated for MTL platform deepin-Intel-SIG: commit d9b904d drm/i915/display: update pll values in sync with Bspec for MTL. MTL Graphics backporting - 2024Q2 Signed-off-by: Ravi Kumar Vodapalli <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 3d890f3 upstream. Add the register that needs to read and written onto for deep pkgc programming. deepin-Intel-SIG: commit 3d890f3 drm/i915/lnl: Add pkgc related register. MTL Graphics backporting - 2024Q2 Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Chaitanya Kumar Borah <[email protected]> Reviewed-by: Vinod Govindapillai <[email protected]> Signed-off-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 810e451 upstream. Looks like TRANS_CHICKEN bit 31 means something totally different depending on the platform: TGL: generate VRR "safe window" for DSB ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR So far we've only set this on ADL/DG2, but when using DSB+VRR we also need to set it on TGL. And a quick test on MTL says it doesn't need this bit for either of those purposes, even though it's still documented as valid in bspec. deepin-Intel-SIG: commit 810e451 drm/i915/vrr: Generate VRR "safe window" for DSB. MTL Graphics backporting - 2024Q2 Cc: [email protected] Fixes: 34d8311 ("drm/i915/dsb: Re-instate DSB for LUT updates") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Animesh Manna <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit 65ea19a upstream. Pass encoder to the _port_to_ddc_pin() functions, and rename to _encoder_to_ddc_pin(). The encoder will be more helpful than just port in the subsequent changes. deepin-Intel-SIG: commit 65ea19a drm/i915/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin(). MTL Graphics backporting - 2024Q2 Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c94debf36816157de1105a186b061fd90dab574a.1710949619.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
commit caf3d74 upstream. UHBR13.5 is not supported in MTL and also the DP2.1 spec says UHBR13.5 is optional. Hence removing UHBR135 from the supported link rates. v2: Reframed the commit message and added link to the issue. deepin-Intel-SIG: commit caf3d74 drm/i915/dp: Remove support for UHBR13.5. MTL Graphics backporting - 2024Q2 Signed-off-by: Arun R Murthy <[email protected]> Fixes: 62618c7 ("drm/i915/mtl: C20 PLL programming") Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit ddf8a8b) Signed-off-by: Rodrigo Vivi <[email protected]> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <[email protected]>
deepin pr auto reviewi915: Fix broken PCI IDs for Tiger Lake and Ryzen 7 4700G git-svn-id: ffe668792ed300d6c2daa1f6eba2e0aa28d7ec6c@311788 91177308-0d34-0410-b5e6-96231b3b80d8 |
matrix-wsk
merged commit 0969b9a
into
deepin-community:linux-6.6.y
3 of 4 checks passed
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This should be the last update of MTL graphics. and this PR is to for graphics bugfix and feature enabling. and at the same time, we expected paving a good way to 15th and 16th graphics backporting.
local testing on Intel SDP MTL machine, works fine.
here are the commit lists from upstream and its kernel version:
final_deepin_graphics_commits.list
3a8ecd4,drm/i915/cx0: Add intel_cx0_get_owned_lane_mask(),2023-08-17 12:25:13,Gustavo Sousa [email protected] v6.7-rc1
8^221^22118^20f5c2e5,drm/i915: Simplify intel_cx0_program_phy_lane() with loop,2023-08-17 12:25:14,Gustavo Sousa [email protected] v6.7-rc1
21^2210226fa3a,drm/i915/cx0: Program vswing only for owned lanes,2023-08-17 12:25:15,Gustavo Sousa [email protected] v6.7-rc1
8^221^22088^2fd279d2,drm/i915/dp_mst: Use output_format to get the final link bpp,2023-08-18 09:42:15,Ankit Nautiyal [email protected] v6.7-rc1
21^2201ae3a70a,drm/i915/regs: split out intel_color_regs.h,2023-08-25 13:12:10,Jani Nikula [email protected] v6.7-rc1
8^221^21668^27f52ca6,drm/i915/color: move CHV CGM pipe mode read to intel_color,2023-08-25 13:12:17,Jani Nikula [email protected] v6.7-rc1
21^2165efe6fcb,drm/i915: move HSW+ gamma mode read to intel_color,2023-08-25 13:12:21,Jani Nikula [email protected] v6.7-rc1
8^221^21648^2cecdea1,drm/i915: move ILK+ CSC mode read to intel_color,2023-08-25 13:12:24,Jani Nikula [email protected] v6.7-rc1
21^2163f56e23e,drm/i915/color: move SKL+ gamma and CSC enable read to intel_color,2023-08-25 13:12:27,Jani Nikula [email protected] v6.7-rc1
8^221^21628^29af09df,drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color,2023-08-25 13:12:31,Jani Nikula [email protected] v6.7-rc1
21^216151152ac,drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim,2023-08-29 13:51:39,Suraj Kandpal [email protected] v6.7-rc1
8^221^21608^2c1464a8,drm/i915: add minimal i915_gem_object_frontbuffer.h,2023-08-31 18:41:34,Jani Nikula [email protected] v6.7-rc1
21^2144113cddd,drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid,2023-09-01 11:47:53,Jani Nikula [email protected] v6.7-rc1
8^221^21388^27218779,drm/edid: add drm_edid_is_digital(),2023-09-01 11:47:53,Jani Nikula [email protected] v6.7-rc1
21^214182b599e,drm/edid: parse source physical address,2023-09-01 11:47:53,Jani Nikula [email protected] v6.7-rc1
8^221^21398^2e1039cd,drm/i915/display: use drm_edid_is_digital(),2023-09-01 11:47:53,Jani Nikula [email protected] v6.7-rc1
21^2140130849f,drm/i915/hdcp: Use intel_connector as argument for hdcp_2_2_capable,2023-09-01 13:17:44,Suraj Kandpal [email protected] v6.7-rc1
8^221^21438^29055e73,drm/i915/dsb: Dump the DSB command buffer when DSB fails,2023-09-07 15:43:29,Ville Syrjälä [email protected] v6.7-rc1
21^2115088ca02,drm/i915/dsb: Avoid corrupting the first register write,2023-09-07 15:44:16,Ville Syrjälä [email protected] v6.7-rc1
8^221^21148^2231b1d6,drm/i915/dsb: Don't use indexed writes when byte enables are not all set,2023-09-07 15:44:41,Ville Syrjälä [email protected] v6.7-rc1
21^211330b98ec,drm/i915: Call the DDC bus i2c adapter "ddc",2023-09-15 14:47:09,Ville Syrjälä [email protected] v6.7-rc1
8^221^2878^2e046d15,drm/i915/hdmi: Use connector->ddc everwhere,2023-09-15 14:48:49,Ville Syrjälä [email protected] v6.7-rc1
21^281ac6dcb6,drm/i915/hdmi: Nuke hdmi->ddc_bus,2023-09-15 14:49:10,Ville Syrjälä [email protected] v6.7-rc1
8^221^2808^231a6575,drm/i915/hdmi: Remove old i2c symlink,2023-09-15 14:50:04,Ville Syrjälä [email protected] v6.7-rc1
21^2796686c30,drm/i915: move more of the display probe to display code,2023-09-15 18:29:05,Jani Nikula [email protected] v6.7-rc1
8^221^2748^2f895e3d,drm/i915: Move psr unlock out from the pipe update critical section,2023-09-20 22:27:08,Ville Syrjälä [email protected] v6.7-rc1
21^267b4ac591,drm/i915: Optimize out redundant M/N updates,2023-09-20 22:29:43,Ville Syrjälä [email protected] v6.7-rc1
8^221^2628^2f0f7ec7,drm/i915: Relocate is_in_vrr_range(),2023-09-20 22:30:08,Ville Syrjälä [email protected] v6.7-rc1
21^2616a38b36,drm/i915: Validate that the timings are within the VRR range,2023-09-20 22:30:55,Ville Syrjälä [email protected] v6.7-rc1
8^221^2608^28f78227,drm/i915: Disable VRR during seamless M/N changes,2023-09-20 22:31:21,Ville Syrjälä [email protected] v6.7-rc1
21^2590ce013a,drm/i915: Update VRR parameters in fastset,2023-09-20 22:31:39,Ville Syrjälä [email protected] v6.7-rc1
8^221^2588^226f03ef,drm/i915: Assert that VRR is off during vblank evasion if necessary,2023-09-20 22:32:22,Ville Syrjälä [email protected] v6.7-rc1
21^25716a9359,drm/i915: Implement transcoder LRR for TGL+,2023-09-20 22:32:55,Ville Syrjälä [email protected] v6.7-rc1
8^221^2568^28dde2e6,drm/i915: Re-order if/else ladder in intel_detect_pch(),2023-09-21 07:39:48,Lucas De Marchi [email protected] v6.7-rc1
21^24965578d0,drm/i915/xe2lpd: Add fake PCH,2023-09-21 07:39:49,Gustavo Sousa [email protected] v6.7-rc1
8^221^2488^2cfeff35,drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation,2023-09-21 07:39:50,Stanislav Lisovskiy [email protected] v6.7-rc1
21^2476f35a04,drm/i915/xe2lpd: Read pin assignment from IOM,2023-09-21 08:18:06,Luca Coelho [email protected] v6.7-rc1
8^221^2408^29d404da,drm/i915/lnl: Add gmbus/ddc support,2023-09-21 08:18:06,Lucas De Marchi [email protected] v6.7-rc1
21^236696c331,drm/i915/xe2lpd: Add support for HPD,2023-09-21 08:18:06,Gustavo Sousa [email protected] v6.7-rc1
8^221^2388^2fa1b97f,drm/i915/dsb: Use non-locked register access,2023-09-27 18:35:29,Ville Syrjälä [email protected] v6.7-rc1
21^225357832b,drm/i915/dsb: Define more DSB bits,2023-09-27 18:36:19,Ville Syrjälä [email protected] v6.7-rc1
8^221^2248^20c1c7a6,drm/i915/dsb: Define the contents of some intstructions bit better,2023-09-27 18:38:17,Ville Syrjälä [email protected] v6.7-rc1
21^223df3b919,drm/i915/dsb: Introduce intel_dsb_noop(),2023-09-27 18:38:40,Ville Syrjälä [email protected] v6.7-rc1
8^221^2228^2e39845d,drm/i915/dsb: Introduce intel_dsb_reg_write_masked(),2023-09-27 18:38:53,Ville Syrjälä [email protected] v6.7-rc1
21^2215053121,drm/i915/dsb: Add support for non-posted DSB registers writes,2023-09-27 18:39:26,Ville Syrjälä [email protected] v6.7-rc1
8^221^2208^25ae0da3,drm/i915/dsb: Load LUTs using the DSB during vblank,2023-09-27 18:40:58,Ville Syrjälä [email protected] v6.7-rc1
21^2187678e08,drm/i915/dsb: Evade transcoder undelayed vblank when using DSB,2023-09-27 18:46:08,Ville Syrjälä [email protected] v6.7-rc1
8^221^2168^2b428328,drm/i915: Introduce skl_watermark_max_latency(),2023-09-27 18:46:22,Ville Syrjälä [email protected] v6.7-rc1
21^21577d8285,drm/i915: Introduce intel_crtc_scanline_to_hw(),2023-09-27 18:47:08,Ville Syrjälä [email protected] v6.7-rc1
8^221^2148^2f83b94d,drm/i915/dsb: Use DEwake to combat PkgC latency,2023-09-27 18:49:06,Ville Syrjälä [email protected] v6.7-rc1
21^213fa7a7a1,drm/i915: Add helper to modeset a set of pipes,2023-09-28 12:52:15,Imre Deak [email protected] v6.7-rc1
8^221^278^2e3b2690,drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late(),2023-09-28 12:52:17,Imre Deak [email protected] v6.7-rc1
21^261050e4c,drm/i915: Factor out a helper to check/compute all the CRTC states,2023-09-28 12:52:19,Imre Deak [email protected] v6.7-rc1
8^221^258^25ed8c7b,drm/i915/mocs: use to_gt() instead of direct &i915->gt,2023-10-04 18:27:33,Jani Nikula [email protected] v6.7-rc1
19^248c788479,drm/i915: Constify the snps/c10x PLL state checkers,2023-10-07 00:12:46,Ville Syrjälä [email protected] v6.7-rc1
8^219^2298^2bcdcae6,drm/i915/dsb: Allocate command buffer from local memory,2023-10-13 16:24:34,Ville Syrjälä [email protected] v6.7-rc1
15^225631b117,drm/i915/dsb: Correct DSB command buffer cache coherency settings,2023-10-13 16:25:30,Ville Syrjälä [email protected] v6.7-rc1
8^215^22421^2b662c19,drm/i915/display: Reset message bus after each read/write operation,2023-10-26 17:48:14,Mika Kahola [email protected] v6.8-rc1
27^2150b0462e9,drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code,2023-10-31 08:31:00,Ville Syrjälä [email protected] v6.8-rc1
21^227^213621^298ed369,drm/i915/dsb: DSB code refactoring,2023-11-16 15:56:53,Animesh Manna [email protected] v6.8-rc1
27^2559d69533,drm/i915: move *_crtc_clock_get() to intel_dpll.c,2023-11-17 14:59:47,Jani Nikula [email protected] v6.8-rc1
21^227^25321^2b1f5279,drm/i915/psr: Move plane sel fetch configuration into plane source files,2023-11-27 07:36:25,Jouni Högander [email protected] v6.8-rc1
24^231562f338,drm/i915/dgfx: DGFX uses direct VBT pin mapping,2023-11-29 14:49:29,Clint Taylor [email protected] v6.8-rc1
21^224^22021^2ef32c3c,drm/i915: correct the input parameter on _intel_dsb_commit(),2023-11-29 19:26:05,heminhong [email protected] v6.8-rc1
24^2226128bec,drm/i915: Stop accessing crtc->state from the flip done irq,2023-12-09 04:13:57,Ville Syrjälä [email protected] v6.8-rc1
21^214^22026^2bac2d7d,drm/i915/display: Take care of VSC select field in video dip ctl register,2023-12-22 08:15:20,Jouni Högander [email protected] v6.9-rc1
25^29593cbc1a,drm/i915/mtl: Add fake PCH for Meteor Lake,2024-01-03 09:17:00,Haridhar Kalvala [email protected] v6.9-rc1
26^225^29326^2c27f010,drm/i915: Disable DSB in Xe KMD,2024-01-05 06:33:31,José Roberto de Souza [email protected] v6.9-rc1
25^282bddacdf,drm/i915: Add additional ARL PCI IDs,2024-01-18 15:24:32,Matt Roper [email protected] v6.9-rc1
26^225^24426^284bf82f,drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+,2024-01-18 15:28:40,Harish Chegondi [email protected] v6.9-rc1
15^29c045bc4,drm/i915: Decouple intel_crtc_vblank_evade_scanlines() from atomic commits,2024-01-22 19:02:58,Ville Syrjälä [email protected] v6.9-rc1
26^225^24126^2bb83f34,drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa,2024-01-22 19:03:11,Ville Syrjälä [email protected] v6.9-rc1
25^240637bda5,drm/i915: Introduce struct intel_vblank_evade_ctx,2024-01-22 19:03:21,Ville Syrjälä [email protected] v6.9-rc1
26^225^23926^2b1f9bc3,drm/i915: Include need_vlv_dsi_wa in intel_vblank_evade_ctx,2024-01-22 19:03:32,Ville Syrjälä [email protected] v6.9-rc1
25^238b5ad7ce,drm/i915: Extract intel_vblank_evade(),2024-01-22 19:03:40,Ville Syrjälä [email protected] v6.9-rc1
26^225^23726^2318ec32,drm/i915: Move the min/max scanline sanity check into intel_vblank_evade(),2024-01-22 19:04:03,Ville Syrjälä [email protected] v6.9-rc1
25^2361de6352,drm/i915: Perform vblank evasion around legacy cursor updates,2024-01-22 19:04:51,Ville Syrjälä [email protected] v6.9-rc1
26^225^23426^26bc41f9,Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation",2024-01-22 19:05:48,Ville Syrjälä [email protected] v6.9-rc1
25^2336d46d09,drm/i915/mtl: Wake GT before sending H2G message,2024-01-23 16:57:47,Vinay Belgaumkar [email protected] v6.9-rc1
26^215^2726^2d5c7854,drm/i915/xe2lpd: Move D2D enable/disable,2024-01-30 07:20:21,Lucas De Marchi [email protected] v6.9-rc1
25^22882195d4,drm/print: move enum drm_debug_category etc. earlier in drm_print.h,2024-02-09 11:51:49,Jani Nikula [email protected] v6.9-rc1
26^223^23826^2dea1731,drm/i915: Move intel_vblank_evade() & co. into intel_vblank.c,2024-01-22 19:04:13,Ville Syrjälä [email protected] v6.9-rc1
25^235d9b904d,drm/i915/display: update pll values in sync with Bspec for MTL,2024-02-14 09:27:25,Ravi Kumar Vodapalli [email protected] v6.9-rc1
26^216^27026^23d890f3,drm/i915/lnl: Add pkgc related register,2024-02-23 11:50:46,Suraj Kandpal [email protected] v6.9-rc1
16^237810e451,drm/i915/vrr: Generate VRR "safe window" for DSB,2024-03-07 18:14:37,Ville Syrjälä [email protected] v6.10-rc1
15^226^218715^265ea19a,drm/i915/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin(),2024-03-21 14:09:58,Jani Nikula [email protected] v6.10-rc1
26^2126caf3d74,drm/i915/dp: Remove support for UHBR13.5,2024-04-02 10:22:42,Arun R Murthy [email protected] v6.9-rc3
25^2^210