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Add support for throwing bad fcs packets
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@wengwz
wengwz committed Jan 27, 2024
1 parent a03b2ad commit 2a9323a
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Showing 10 changed files with 835 additions and 109 deletions.
37 changes: 34 additions & 3 deletions fpga/bsv/CmacRecvMonitor.bsv
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
typedef 32 PKT_COUNT_WIDTH;
typedef 32 BEAT_COUNT_WIDTH;
typedef 32 CYCLE_COUNT_WIDTH;
typedef 3 RX_FCS_WIDTH;
typedef 16 MON_COUNT_WIDTH;
typedef 600000000 IDLE_CYCLE_NUM;

interface CmacRecvMonitor;
Expand All @@ -13,18 +15,28 @@ interface CmacRecvMonitor;
method Bit#(BEAT_COUNT_WIDTH) lostBeatCounterOut;
(* always_ready, always_enabled *)
method Bit#(BEAT_COUNT_WIDTH) totalBeatCounterOut;
(* always_ready, always_enabled *)
method Bit#(MON_COUNT_WIDTH) badFCSCounterOut;
(* always_ready, always_enabled *)
method Bit#(MON_COUNT_WIDTH) maxPktSizeOut;
endinterface

(* synthesize, default_clock_osc = "clk", default_reset = "reset" *)
module mkCmacRecvMonitor#(
Bool valid,
Bool ready,
Bool last
Bool last,
Bool user,
Bit#(RX_FCS_WIDTH) badFCS,
Bit#(RX_FCS_WIDTH) stompedFCS
)(CmacRecvMonitor);
Reg#(Bit#(PKT_COUNT_WIDTH )) pktCounter <- mkReg(0);
Reg#(Bit#(BEAT_COUNT_WIDTH)) lostBeatCounter <- mkReg(0);
Reg#(Bit#(BEAT_COUNT_WIDTH)) totalBeatCounter <- mkReg(0);
Reg#(Bit#(CYCLE_COUNT_WIDTH)) idleCycleCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH)) badFCSCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH)) pktSizeCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH)) maxPktSizeReg <- mkReg(0);
Reg#(Bool) isMonitorIdle <- mkReg(False);

rule countPkt;
Expand All @@ -33,11 +45,22 @@ module mkCmacRecvMonitor#(
pktCounter <= last ? 1 : 0;
lostBeatCounter <= ready ? 0 : 1;
totalBeatCounter <= 1;
maxPktSizeReg <= 0;
pktSizeCounter <= 1;
end
else begin
totalBeatCounter <= totalBeatCounter + 1;
if (last) pktCounter <= pktCounter + 1;
if (!ready) lostBeatCounter <= lostBeatCounter + 1;
if (!ready) lostBeatCounter <= lostBeatCounter + 1;
if (last) begin
pktCounter <= pktCounter + 1;
pktSizeCounter <= 0;
if ((pktSizeCounter + 1) > maxPktSizeReg) begin
maxPktSizeReg <= pktSizeCounter + 1;
end
end
else begin
pktSizeCounter <= pktSizeCounter + 1;
end
end
isMonitorIdle <= False;
idleCycleCounter <= 0;
Expand All @@ -52,8 +75,16 @@ module mkCmacRecvMonitor#(
end
endrule

rule countStatus;
if (user) begin
badFCSCounter <= badFCSCounter + 1;
end
endrule

method Bool isMonitorIdleOut = isMonitorIdle;
method Bit#(PKT_COUNT_WIDTH) pktCounterOut = pktCounter;
method Bit#(BEAT_COUNT_WIDTH) lostBeatCounterOut = lostBeatCounter;
method Bit#(BEAT_COUNT_WIDTH) totalBeatCounterOut = totalBeatCounter;
method Bit#(MON_COUNT_WIDTH) badFCSCounterOut = badFCSCounter;
method Bit#(MON_COUNT_WIDTH) maxPktSizeOut = maxPktSizeReg;
endmodule
51 changes: 37 additions & 14 deletions fpga/bsv/CmacSendMonitor.bsv
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
typedef 32 PKT_COUNT_WIDTH;
typedef 32 BEAT_COUNT_WIDTH;
typedef 32 CYCLE_COUNT_WIDTH;
typedef 32 PKT_SIZE_WIDTH;
typedef 16 MON_COUNT_WIDTH;
typedef 600000000 IDLE_CYCLE_NUM;

interface CmacSendMonitor;
Expand All @@ -10,20 +10,29 @@ interface CmacSendMonitor;
(* always_ready, always_enabled *)
method Bit#(PKT_COUNT_WIDTH) pktCounterOut;
(* always_ready, always_enabled *)
method Bit#(PKT_SIZE_WIDTH) pktSizeCounterOut;
method Bit#(MON_COUNT_WIDTH) maxPktSizeOut;
(* always_ready, always_enabled *)
method Bit#(BEAT_COUNT_WIDTH) totalBeatCounterOut;
(* always_ready, always_enabled *)
method Bit#(MON_COUNT_WIDTH) overflowCounterOut;
(* always_ready, always_enabled *)
method Bit#(MON_COUNT_WIDTH) underflowCounterOut;
endinterface

(* synthesize, default_clock_osc = "clk", default_reset = "reset" *)
module mkCmacSendMonitor#(
Bool valid,
Bool ready,
Bool last
Bool last,
Bool txOverflow,
Bool txUnderflow
)(CmacSendMonitor);
Reg#(Bit#(PKT_COUNT_WIDTH )) pktCounter <- mkReg(0);
Reg#(Bit#(PKT_SIZE_WIDTH )) pktSizeCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH )) pktSizeCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH )) maxPktSizeReg <- mkReg(0);
Reg#(Bit#(BEAT_COUNT_WIDTH)) totalBeatCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH)) overflowCounter <- mkReg(0);
Reg#(Bit#(MON_COUNT_WIDTH)) underflowCounter <- mkReg(0);
Reg#(Bit#(CYCLE_COUNT_WIDTH)) idleCycleCounter <- mkReg(0);
Reg#(Bool) isMonitorIdle <- mkReg(False);

Expand All @@ -32,21 +41,24 @@ module mkCmacSendMonitor#(
if (isMonitorIdle) begin
totalBeatCounter <= 1;
pktCounter <= last ? 1 : 0;
pktSizeCounter <= 1;
maxPktSizeReg <= 0;
end
else begin
totalBeatCounter <= totalBeatCounter + 1;
if (last) pktCounter <= pktCounter + 1;
if (last) begin
pktCounter <= pktCounter + 1;
pktSizeCounter <= 0;
if ((pktSizeCounter + 1) > maxPktSizeReg) begin
maxPktSizeReg <= pktSizeCounter + 1;
end
end
else begin
pktSizeCounter <= pktSizeCounter + 1;
end
end

isMonitorIdle <= False;
idleCycleCounter <= 0;

if (last) begin
pktSizeCounter <= 0;
end
else begin
pktSizeCounter <= pktSizeCounter + 1;
end
end
else begin
if (idleCycleCounter < fromInteger(valueOf(IDLE_CYCLE_NUM))) begin
Expand All @@ -58,8 +70,19 @@ module mkCmacSendMonitor#(
end
endrule

rule countStatus;
if (txOverflow) begin
overflowCounter <= overflowCounter + 1;
end
if (txUnderflow) begin
underflowCounter <= underflowCounter + 1;
end
endrule

method Bool isMonitorIdleOut = isMonitorIdle;
method Bit#(PKT_COUNT_WIDTH) pktCounterOut = pktCounter;
method Bit#(PKT_SIZE_WIDTH) pktSizeCounterOut = pktSizeCounter;
method Bit#(MON_COUNT_WIDTH) maxPktSizeOut = maxPktSizeReg;
method Bit#(BEAT_COUNT_WIDTH) totalBeatCounterOut = totalBeatCounter;
method Bit#(MON_COUNT_WIDTH) overflowCounterOut = overflowCounter;
method Bit#(MON_COUNT_WIDTH) underflowCounterOut = underflowCounter;
endmodule
24 changes: 16 additions & 8 deletions fpga/bsv/XdmaUdpCmacPerfMonitor.bsv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ import AxiStreamTypes :: *;

typedef 32 PERF_CYCLE_COUNT_WIDTH;
typedef 32 PERF_BEAT_COUNT_WIDTH;
typedef 500000000 CLOCK_FREQUENCY;
typedef 32 PKT_NUM_COUNT_WIDTH;
typedef 32 PKT_SIZE_COUNT_WIDTH;

Expand Down Expand Up @@ -64,6 +63,8 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
Reg#(Bool) perfCycleCountFullTx[2] <- mkCReg(2, False);
Reg#(Bool) perfCycleCountFullRx <- mkReg(False);

Reg#(Bit#(PERF_CYCLE_COUNT_WIDTH)) maxPerfCycleNumReg <- mkReg(0);

Reg#(Bit#(PERF_CYCLE_COUNT_WIDTH)) perfCycleCounterTx <- mkReg(0);
Reg#(Bit#(PERF_BEAT_COUNT_WIDTH)) perfBeatCounterTx <- mkReg(0);
Reg#(Bit#(PERF_BEAT_COUNT_WIDTH)) totalBeatCounterTx <- mkReg(0);
Expand Down Expand Up @@ -93,8 +94,10 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
xdmaAxiStreamInBuf.deq;
Bit#(PKT_SIZE_COUNT_WIDTH) pktSize = truncate(perfMonConfig);
let pktInterval = perfMonConfig >> valueOf(PKT_SIZE_COUNT_WIDTH);
let maxPerfCycleNum = pktInterval >> valueOf(PERF_CYCLE_COUNT_WIDTH);
pktSizeReg <= pktSize;
pktIntervalReg <= truncate(pktInterval);
maxPerfCycleNumReg <= truncate(maxPerfCycleNum);
if (pktSize != 0) begin
sendPktEnableReg <= True;
recvPktEnableReg <= True;
Expand All @@ -116,7 +119,7 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
rule sendPacket if (sendPktEnableReg && !isPktIntervalReg);

let axiFrame = AxiStream512 {
tData: {sendPktNumCounter, 0} | {0, sendPktBeatCounter},
tData: {sendPktBeatCounter, 0, sendPktBeatCounter},
tKeep: setAllBits,
tLast: False,
tUser: 0
Expand Down Expand Up @@ -157,7 +160,7 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
rule countPerfCycleTx if (sendPktEnableReg);
if (!perfCycleCountFullTx[0]) begin
perfCycleCounterTx <= perfCycleCounterTx + 1;
if (perfCycleCounterTx == fromInteger(valueOf(CLOCK_FREQUENCY))) begin
if (perfCycleCounterTx == maxPerfCycleNumReg) begin
perfCycleCountFullTx[0] <= True;
end
end
Expand All @@ -172,9 +175,9 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
end

let isRecvBeatError = False;
let pktIdxMismatch = truncateLSB(axiFrame.tData) != recvPktNumCounter[0];
let beatIdxMismatch = truncate(axiFrame.tData) != recvPktBeatCounter;
if (pktIdxMismatch || beatIdxMismatch) begin
let headMismatch = truncateLSB(axiFrame.tData) != recvPktBeatCounter;
let tailMismatch = truncate(axiFrame.tData) != recvPktBeatCounter;
if (headMismatch || tailMismatch) begin
isRecvBeatError = True;
end

Expand All @@ -184,10 +187,15 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
errPktNumCounter[0] <= errPktNumCounter[0] + 1;
end
isPktHasErrorReg <= False;
recvPktBeatCounter <= 0;
end
else begin
if (!isPktHasErrorReg) isPktHasErrorReg <= isRecvBeatError;
end

if (recvPktBeatCounter == pktSizeReg - 1) begin
recvPktBeatCounter <= 0;
end
else begin
recvPktBeatCounter <= recvPktBeatCounter + 1;
end
isRecvFirstPktReg[0] <= True;
Expand All @@ -196,7 +204,7 @@ module mkXdmaUdpCmacPerfMonitor(XdmaUdpCmacPerfMonitor);
rule countPerfCycleRx if (recvPktEnableReg);
if (isRecvFirstPktReg[1] && !perfCycleCountFullRx) begin
perfCycleCounterRx <= perfCycleCounterRx + 1;
if (perfCycleCounterRx == fromInteger(valueOf(CLOCK_FREQUENCY))) begin
if (perfCycleCounterRx == maxPerfCycleNumReg) begin
perfCycleCountFullRx <= True;
recvPktEnableReg <= False;
end
Expand Down
Empty file added fpga/bsv/XdmaUdpTxPerfMonitor.bsv
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