[config] fix rookidee dlen

designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml

@@ -1,5 +1,5 @@
 [rookidee]
-cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
+cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
 [blastoise]
 cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
 

designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml

@@ -1,5 +1,5 @@
 [rookidee]
-cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
+cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
 [blastoise]
 cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"
 

difftest/dpi_t1rocketemu/src/bus.rs

@@ -65,15 +65,23 @@ impl ShadowBus {
   }
 
   // size: 1 << arsize
+  // nr_beat: arlen + 1
   // bus_size: AXI bus width in bytes
   // return: Vec<u8> with len=bus_size
-  // if size < bus_size, the result is padded due to AXI narrow transfer rules
-  pub fn read_mem_axi(&self, addr: u32, size: u32, bus_size: u32) -> Vec<u8> {
+  // if `size < bus_size`, the result is padded due to AXI narrow transfer rules
+  // if `size < bus_size`, then `nr_beat == 1` must hold, narrow burst is not supported
+  pub fn read_mem_axi(&self, addr: u32, size: u32, bus_size: u32, nr_beat: u32) -> Vec<u8> {
     assert!(
       addr % size == 0 && bus_size % size == 0,
       "unaligned access addr={addr:#x} size={size}B dlen={bus_size}B"
     );
 
+    assert!(nr_beat > 0);
+    assert!(
+      nr_beat == 1 || size == bus_size,
+      "narrow burst is not supported"
+    );
+
     let start = addr as usize;
     let end = (addr + size) as usize;
 
@@ -84,7 +92,7 @@ impl ShadowBus {
     match handler {
       Some(ShadowBusDevice { base, size: _, device }) => {
         let offset = start - *base;
-        let data = device.read_mem(offset, size as usize);
+        let data = device.read_mem(offset, (size * nr_beat) as usize);
 
         if size < bus_size {
           let mut data_padded = vec![0; bus_size as usize];

difftest/dpi_t1rocketemu/src/dpi.rs

@@ -279,7 +279,7 @@ unsafe extern "C" fn axi_read_instructionFetchAXI(
   arprot={arprot}, arqos={arqos}, arregion={arregion})"
   );
   TARGET.with(|driver| {
-    let response = driver.axi_read_instruction_fetch(araddr as u32, arsize as u64);
+    let response = driver.axi_read_instruction_fetch(araddr as u32, arsize as u32, arlen as u32);
     fill_axi_read_payload(payload, driver.dlen, &response);
   });
 }

difftest/dpi_t1rocketemu/src/drive.rs

@@ -132,7 +132,7 @@ impl Driver {
 
   pub(crate) fn axi_read_high_bandwidth(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
     let size = 1 << arsize;
-    let data = self.shadow_bus.read_mem_axi(addr, size, self.dlen / 8);
+    let data = self.shadow_bus.read_mem_axi(addr, size, self.dlen / 8, 1);
     let data_hex = hex::encode(&data);
     self.last_commit_cycle = get_t();
     trace!(
@@ -162,7 +162,7 @@ impl Driver {
   pub(crate) fn axi_read_high_outstanding(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
     let size = 1 << arsize;
     assert!(size <= 4);
-    let data = self.shadow_bus.read_mem_axi(addr, size, 4);
+    let data = self.shadow_bus.read_mem_axi(addr, size, 4, 1);
     let data_hex = hex::encode(&data);
     self.last_commit_cycle = get_t();
     trace!(
@@ -192,7 +192,7 @@ impl Driver {
   pub(crate) fn axi_read_load_store(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
     let size = 1 << arsize;
     let bus_size = if size == 32 { 32 } else { 4 };
-    let data = self.shadow_bus.read_mem_axi(addr, size, bus_size);
+    let data = self.shadow_bus.read_mem_axi(addr, size, bus_size, 1);
     let data_hex = hex::encode(&data);
     self.last_commit_cycle = get_t();
     trace!(
@@ -231,9 +231,14 @@ impl Driver {
     }
   }
 
-  pub(crate) fn axi_read_instruction_fetch(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
+  pub(crate) fn axi_read_instruction_fetch(
+    &mut self,
+    addr: u32,
+    arsize: u32,
+    arlen: u32,
+  ) -> AxiReadPayload {
     let size = 1 << arsize;
-    let data = self.shadow_bus.read_mem_axi(addr, size, 32);
+    let data = self.shadow_bus.read_mem_axi(addr, size, 4, arlen + 1);
     let data_hex = hex::encode(&data);
     trace!(
       "[{}] axi_read_instruction_fetch (addr={addr:#x}, size={size}, data={data_hex})",

rocketv/src/Frontend.scala

@@ -113,7 +113,7 @@ case class FrontendParameter(
     exec = exec,
     sideEffects = sideEffects
   )
-  val rowBits:                   Int                 = blockBytes * 8
+  val rowBits:                   Int                 = fetchBytes * 8
   val instructionFetchParameter: AXI4BundleParameter = AXI4BundleParameter(
     idWidth = 1,
     dataWidth = rowBits,

rocketv/src/HellaCache.scala

@@ -1074,7 +1074,7 @@ class HellaCache(val parameter: HellaCacheParameter)
       0.U,
       (parameter.cacheBlockBytes * 8 / parameter.loadStoreParameter.dataWidth - 1).U
     )
-    arQueue.enq.bits.size  := Mux(s2_uncached, a_size, parameter.lgCacheBlockBytes.U)
+    arQueue.enq.bits.size  := Mux(s2_uncached, a_size, log2Ceil(parameter.loadStoreParameter.dataWidth / 8).U)
     arQueue.enq.bits.id    := Mux(s2_uncached, a_source, 0.U)
     io.loadStoreAXI.ar <> arQueue.deq
 
@@ -1335,7 +1335,7 @@ class HellaCache(val parameter: HellaCacheParameter)
       awQueue.enq.valid     := true.B
       awQueue.enq.bits.addr := releaseAddress >> parameter.lgCacheBlockBytes << parameter.lgCacheBlockBytes
       awQueue.enq.bits.len  := (parameter.cacheBlockBytes * 8 / parameter.loadStoreParameter.dataWidth - 1).U
-      awQueue.enq.bits.size := parameter.lgCacheBlockBytes.U
+      awQueue.enq.bits.size := log2Ceil(parameter.loadStoreParameter.dataWidth / 8).U
       awQueue.enq.bits.id   := (mmioOffset - 1).U
     }
 

rocketv/src/ICache.scala

@@ -10,7 +10,14 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.properties.{AnyClassType, Class, ClassType, Property}
 import chisel3.util.random.LFSR
 import chisel3.util._
-import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4ROIrrevocable, AXI4RWIrrevocable}
+import org.chipsalliance.amba.axi4.bundle.{
+  AXI4BundleParameter,
+  AXI4ChiselBundle,
+  AXI4ROIrrevocable,
+  AXI4RWIrrevocable,
+  R,
+  W
+}
 import org.chipsalliance.dwbb.stdlib.queue.Queue
 
 case class ICacheParameter(
@@ -41,7 +48,7 @@ case class ICacheParameter(
   val hasUncorrekoctable:        Boolean                     = itimBaseAddr.nonEmpty && dataCode.canDetect
   val isDM:                      Boolean                     = nWays == 1
   // axi data with
-  val rowBits:                   Int                         = blockBytes * 8
+  val rowBits:                   Int                         = fetchBytes * 8
   val refillCycles:              Int                         = blockBytes * 8 / rowBits
   val blockOffBits:              Int                         = log2Up(blockBytes)
   val idxBits:                   Int                         = log2Up(nSets)
@@ -348,10 +355,24 @@ class ICache(val parameter: ICacheParameter)
   io.req.ready := !(refill_one_beat || s0_slaveValid || s3_slaveValid)
   s1_valid     := s0_valid
 
-  //  val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)
-  val d_done:     Bool = io.instructionFetchAXI.r.valid && io.instructionFetchAXI.r.bits.last
-  // todo: burst index always == 0?
-  val refill_cnt: UInt = 0.U
+  // tod: package
+  def axiHelper(x: AXI4ChiselBundle, fire: Bool): (Bool, Bool, Bool, UInt) = {
+    // same as len
+    val count = RegInit(0.U(8.W))
+    val first = count === 0.U
+    val last: Bool = x match {
+      case r: R => r.last
+      case w: W => w.last
+      case _ => true.B
+    }
+    val done = last && fire
+    when(fire) {
+      count := Mux(last, 0.U, count + 1.U)
+    }
+    (first, last, done, count)
+  }
+
+  val (_, _, d_done, d_refill_count) = axiHelper(io.instructionFetchAXI.r.bits, io.instructionFetchAXI.r.fire)
 
   /** at last beat of `tl_out.d.fire`, finish refill. */
   val refill_done = refill_one_beat && d_done
@@ -394,7 +415,7 @@ class ICache(val parameter: ICacheParameter)
 
   /** wire indicates the ongoing GetAckData transaction is corrupted. */
   //  todo: tl_out.d.bits.corrupt -> false.B
-  val refillError: Bool = false.B || (refill_cnt > 0.U && accruedRefillError)
+  val refillError: Bool = false.B || (d_refill_count > 0.U && accruedRefillError)
   val enc_tag = tECC.encode(Cat(refillError, refill_tag))
   icacheTagSRAM.readwritePorts.foreach { ramPort =>
     ramPort.enable    := s0_valid || refill_done
@@ -542,8 +563,13 @@ class ICache(val parameter: ICacheParameter)
   for ((data_array, i) <- icacheDataSRAM.zipWithIndex) {
 
     /** bank match (vaddr[2]) */
-    def wordMatch(addr: UInt): Bool =
-      addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+    def wordMatch(addr: UInt): Bool = {
+      if (io.instructionFetchAXI.r.bits.data.getWidth == wordBits) { true.B }
+      else {
+        addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+      }
+    }
+
     // TODO: if we have last? do we need refillCycles?
     def row(addr: UInt) = addr(untagBits - 1, blockOffBits - log2Ceil(refillCycles))
 
@@ -559,7 +585,7 @@ class ICache(val parameter: ICacheParameter)
       // I$ refill. refill_idx[2:0] is the beats
       Mux(
         refill_one_beat,
-        (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
+        (refill_idx << log2Ceil(refillCycles)) | d_refill_count,
         // ITIM write.
         Mux(
           s3_slaveValid,
@@ -791,8 +817,8 @@ class ICache(val parameter: ICacheParameter)
   arQueue.enq.bits       := DontCare
   arQueue.enq.bits.id    := 0.U
   arQueue.enq.bits.addr  := (refill_paddr >> blockOffBits) << blockOffBits
-  arQueue.enq.bits.size  := log2Up(parameter.blockBytes).U
-  arQueue.enq.bits.len   := 0.U
+  arQueue.enq.bits.size  := log2Up(parameter.instructionFetchParameter.dataWidth / 8).U
+  arQueue.enq.bits.len   := (parameter.blockBytes * 8 / parameter.instructionFetchParameter.dataWidth - 1).U
   arQueue.enq.bits.burst := 1.U
   io.instructionFetchAXI.ar <> arQueue.deq
 

rocketv/src/RocketCore.scala

@@ -47,7 +47,8 @@ class RocketProbe(param: RocketParameter) extends Bundle {
   val waitWen:        Bool                       = new Bool()
   val waitWaddr:      UInt                       = UInt(param.lgNXRegs.W)
   val isVectorCommit: Bool                       = Bool()
-  val isVectorWrite:  Bool                       = Bool()
+  val vectorWriteRD:  Bool                       = Bool()
+  val vectorWriteFD:  Bool                       = Bool()
   val idle:           Bool                       = Bool()
   // fpu score board
   val fpuScoreboard:  Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe)
@@ -1637,7 +1638,8 @@ class Rocket(val parameter: RocketParameter)
           wbRegValid && wbRegDecodeOutput(parameter.decoderParameter.vector) &&
           !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
         }.getOrElse(false.B)
-        probeWire.isVectorWrite  := t1RetireQueue.map(q => q.deq.fire).getOrElse(false.B)
+        probeWire.vectorWriteRD  := t1RetireQueue.map(q => q.deq.fire && !q.deq.bits.isFp).getOrElse(false.B)
+        probeWire.vectorWriteFD  := t1RetireQueue.map(q => q.deq.fire && q.deq.bits.isFp).getOrElse(false.B)
         probeWire.idle           := vectorEmpty
 
         probeWire.wbRegPc := wbRegPc

t1rocketemu/src/TestBench.scala

@@ -109,7 +109,7 @@ class TestBench(val parameter: T1RocketTileParameter)
         name = "instructionFetchAXI",
         axiParameter = instFetchAXI.parameter,
         outstanding = 4,
-        readPayloadSize = 1,
+        readPayloadSize = 8,
         writePayloadSize = 1
       )
     ).suggestName("axi4_channel2_instructionFetchAXI")
@@ -119,7 +119,7 @@ class TestBench(val parameter: T1RocketTileParameter)
   }
   instFetchAgent.io.clock := clock
   instFetchAgent.io.reset     := reset
-  instFetchAgent.io.channelId := 0.U
+  instFetchAgent.io.channelId := 2.U
   instFetchAgent.io.gateRead  := false.B
   instFetchAgent.io.gateWrite := false.B
 
@@ -164,7 +164,7 @@ class TestBench(val parameter: T1RocketTileParameter)
   // output the probes
   // rocket reg write
   when(
-    rocketProbe.rfWen && !rocketProbe.isVectorWrite && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U)
+    rocketProbe.rfWen && !rocketProbe.vectorWriteRD && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U)
   )(
     printf(
       cf"""{"event":"RegWrite","idx":${rocketProbe.rfWaddr},"data":"${rocketProbe.rfWdata}%x","cycle":${simulationTime}}\n"""
@@ -190,7 +190,7 @@ class TestBench(val parameter: T1RocketTileParameter)
           )
         )
       )
-      val isVectorForLLWrite = RegNext(rocketProbe.isVectorWrite, false.B)
+      val isVectorForLLWrite = RegNext(rocketProbe.vectorWriteFD, false.B)
 
       fpToIEEE.io.clock           := clock
       fpToIEEE.io.reset           := reset