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fpu decode #749

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fpu decode #749

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c50cfcb
[rocketv] Try to separate the floating point decode, 'fp' represents …
qinjun-li Aug 27, 2024
0c9730f
[rocketv] All vector floating-point operations use the dynamic roundi…
qinjun-li Sep 5, 2024
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5 changes: 3 additions & 2 deletions rocketv/src/Decoder.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -165,14 +165,15 @@ case class DecoderParameter(
object fp extends BoolDecodeField[RocketDecodePattern] {
override def name: String = "fp"

override def genTable(op: RocketDecodePattern): BitPat = op.instruction.instructionSet.name match {
override def genTable(op: RocketDecodePattern): BitPat = (op.instruction.instructionSet.name, op) match {
// format: off
case s if Seq(
case (s, _) if Seq(
"rv_d", "rv64_d",
"rv_f", "rv64_f",
"rv_q", "rv64_q",
"rv_zfh", "rv64_zfh", "rv_d_zfh", "rv_q_zfh",
).contains(s) => y
case (_, p) if p.vectorReadFRegFile => y
case _ => n
// format: on
}
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7 changes: 3 additions & 4 deletions rocketv/src/FPU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -379,10 +379,9 @@ class FPU(val parameter: FPUParameter)

def isOneOf(x: UInt, s: Seq[UInt]): Bool = VecInit(s.map(x === _)).asUInt.orR
// we don't currently support round-max-magnitude (rm=4)
io.core.illegal_rm := isOneOf(io.core.inst(14, 12), Seq(5.U, 6.U)) || io.core.inst(
14,
12
) === 7.U && io.core.fcsr_rm >= 5.U
io.core.illegal_rm :=
(isOneOf(io.core.inst(14, 12), Seq(5.U, 6.U)) && io.core.inst(6, 0) =/= "b1010111".U) ||
io.core.inst(14, 12) === 7.U && io.core.fcsr_rm >= 5.U

if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
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14 changes: 2 additions & 12 deletions rocketv/src/RocketCore.scala
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Expand Up @@ -1409,13 +1409,7 @@ class Rocket(val parameter: RocketParameter)
csr.io.csrStall || csr.io.singleStep && (exRegValid || memRegValid || wbRegValid) ||
idCsrEn && csr.io.decode(0).fpCsr && !io.fpu.map(_.fcsr_rdy).getOrElse(false.B) || io.traceStall ||
!clockEnable ||
Option
.when(usingFPU)(
(idDecodeOutput(parameter.decoderParameter.fp) || idDecodeOutput(
parameter.decoderParameter.vectorReadFRs1
)) && idStallFpu
)
.getOrElse(false.B) ||
Option.when(usingFPU)(idDecodeOutput(parameter.decoderParameter.fp) && idStallFpu).getOrElse(false.B) ||
idDecodeOutput(parameter.decoderParameter.mem) && dcacheBlocked || // reduce activity during D$ misses
Option
.when(usingMulDiv)(
Expand Down Expand Up @@ -1509,11 +1503,7 @@ class Rocket(val parameter: RocketParameter)
io.fpu.foreach { fpu =>
fpuDecoder.get.io.instruction := idInstruction
fpu.dec := fpuDecoder.get.io.output
fpu.valid := !ctrlKilled && (
idDecodeOutput(parameter.decoderParameter.fp) ||
// vector read frs1
(fpu.dec.ren1 && idDecodeOutput(parameter.decoderParameter.vector))
)
fpu.valid := !ctrlKilled && idDecodeOutput(parameter.decoderParameter.fp)
fpu.killx := ctrlKillx
fpu.killm := killmCommon
fpu.inst := idInstruction
Expand Down