Switch to Layer API

ipemu/src/TestBench.scala

@@ -27,6 +27,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
     extends RawModule
     with ImplicitClock
     with ImplicitReset {
+  layer.enable(layers.Verification)
   val omInstance: Instance[TestBenchOM] = Instantiate(new TestBenchOM)
   val omType:     ClassType = omInstance.toDefinition.getClassType
   @public

t1/src/T1.scala

@@ -327,7 +327,7 @@ class T1Interface(parameter: T1Parameter) extends Record {
       "highBandwidthLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter),
       "indexedLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter.copy(dataWidth=32)),
       "om" -> Output(Property[AnyClassType]()),
-      "t1Probe" -> Output(Probe(new T1Probe(parameter))),
+      "t1Probe" -> Output(Probe(new T1Probe(parameter), layers.Verification)),
     ) 
   )
 }
@@ -1721,26 +1721,27 @@ class T1(val parameter: T1Parameter)
   // don't care有可能会导致先读后写失败
   maskUnitReadVec.foreach(_.bits.instructionIndex := slots.last.record.instructionIndex)
 
-  /**
-    * Probes
-    */
-  val probeWire = Wire(new T1Probe(parameter))
-  define(io.t1Probe, ProbeValue(probeWire))
-  probeWire.instructionCounter := instructionCounter
-  probeWire.instructionIssue := requestRegDequeue.fire
-  probeWire.issueTag := requestReg.bits.instructionIndex
-  probeWire.retireValid := retire
-  // maskUnitWrite maskUnitWriteReady
-  probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
-  probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex
-  probeWire.writeQueueEnqMask := maskUnitWrite.bits.mask
-  probeWire.instructionValid := maskAnd(
-    !slots.last.state.sMaskUnitExecution && !slots.last.state.idle,
-    indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)).asUInt
-  probeWire.responseCounter := responseCounter
-  probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
-  probeWire.lsuProbe := probe.read(lsu.lsuProbe)
-
+  layer.block(layers.Verification) {
+    /**
+      * Probes
+      */
+    val probeWire = Wire(new T1Probe(parameter))
+    define(io.t1Probe, ProbeValue(probeWire))
+    probeWire.instructionCounter := instructionCounter
+    probeWire.instructionIssue := requestRegDequeue.fire
+    probeWire.issueTag := requestReg.bits.instructionIndex
+    probeWire.retireValid := retire
+    // maskUnitWrite maskUnitWriteReady
+    probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
+    probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex
+    probeWire.writeQueueEnqMask := maskUnitWrite.bits.mask
+    probeWire.instructionValid := maskAnd(
+      !slots.last.state.sMaskUnitExecution && !slots.last.state.idle,
+      indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)).asUInt
+    probeWire.responseCounter := responseCounter
+    probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
+    probeWire.lsuProbe := probe.read(lsu.lsuProbe)
+  }
 
   // new V Request from core
   // val requestValidProbe: Bool = IO(Output(Probe(Bool())))

t1/src/laneStage/LaneStage1.scala

@@ -385,43 +385,45 @@ class LaneStage1(parameter: LaneParameter, isLastSlot: Boolean) extends Module {
   stageValid := pipeQueue.io.deq.valid
   val stageFinish = !stageValid
 
+  // TODO: gather these logic into a Probe Bundle
   @public
-  val dequeueReadyProbe = IO(Output(Probe(Bool())))
+  val dequeueReadyProbe = IO(Output(Probe(Bool(), layers.Verification)))
   @public
-  val dequeueValidProbe = IO(Output(Probe(Bool())))
+  val dequeueValidProbe = IO(Output(Probe(Bool(), layers.Verification)))
   @public
-  val hasDataOccupiedProbe = IO(Output(Probe(Bool())))
+  val hasDataOccupiedProbe = IO(Output(Probe(Bool(), layers.Verification)))
   @public
-  val stageFinishProbe = IO(Output(Probe(Bool())))
+  val stageFinishProbe = IO(Output(Probe(Bool(), layers.Verification)))
   @public
-  val readFinishProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool()))))
+  val readFinishProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool(), layers.Verification))))
   @public
-  val sSendCrossReadResultLSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool()))))
+  val sSendCrossReadResultLSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool(), layers.Verification))))
   @public
-  val sSendCrossReadResultMSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool()))))
+  val sSendCrossReadResultMSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool(), layers.Verification))))
   @public
-  val wCrossReadLSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool()))))
+  val wCrossReadLSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool(), layers.Verification))))
   @public
-  val wCrossReadMSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool()))))
+  val wCrossReadMSBProbe = Option.when(isLastSlot)(IO(Output(Probe(Bool(), layers.Verification))))
   @public
-  val vrfReadRequestProbe: Seq[(Bool, Bool)] = Seq.fill(3)((IO(Output(Probe(Bool()))),IO(Output(Probe(Bool())))))
-
-
-  define(dequeueReadyProbe, ProbeValue(dequeue.ready))
-  define(dequeueValidProbe, ProbeValue(dequeue.valid))
-  define(hasDataOccupiedProbe, ProbeValue(stageValid))
-  define(stageFinishProbe, ProbeValue(stageFinish))
-
-  if (isLastSlot) {
-    readFinishProbe.foreach(p => define(p, ProbeValue(dataQueueVs2.io.deq.valid)))
-    sSendCrossReadResultLSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.sSendCrossReadResultLSB)))
-    sSendCrossReadResultMSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.sSendCrossReadResultMSB)))
-    wCrossReadLSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.wCrossReadLSB)))
-    wCrossReadMSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.wCrossReadMSB)))
-  }
+  val vrfReadRequestProbe: Seq[(Bool, Bool)] = Seq.fill(3)((IO(Output(Probe(Bool(), layers.Verification))),IO(Output(Probe(Bool(), layers.Verification)))))
+
+  layer.block(layers.Verification) {
+    define(dequeueReadyProbe, ProbeValue(dequeue.ready))
+    define(dequeueValidProbe, ProbeValue(dequeue.valid))
+    define(hasDataOccupiedProbe, ProbeValue(stageValid))
+    define(stageFinishProbe, ProbeValue(stageFinish))
+
+    if (isLastSlot) {
+      readFinishProbe.foreach(p => define(p, ProbeValue(dataQueueVs2.io.deq.valid)))
+      sSendCrossReadResultLSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.sSendCrossReadResultLSB)))
+      sSendCrossReadResultMSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.sSendCrossReadResultMSB)))
+      wCrossReadLSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.wCrossReadLSB)))
+      wCrossReadMSBProbe.foreach(p => define(p, ProbeValue(crossReadUnitOp.get.crossWriteState.wCrossReadMSB)))
+    }
 
-  vrfReadRequestProbe.zipWithIndex.foreach { case((ready, valid), i) =>
-    define(ready, ProbeValue(vrfReadRequest(i).ready))
-    define(valid, ProbeValue(vrfReadRequest(i).valid))
+    vrfReadRequestProbe.zipWithIndex.foreach { case ((ready, valid), i) =>
+      define(ready, ProbeValue(vrfReadRequest(i).ready))
+      define(valid, ProbeValue(vrfReadRequest(i).valid))
+    }
   }
 }

t1/src/lsu/LSU.scala

@@ -246,9 +246,7 @@ class LSU(param: LSUParameter) extends Module {
   )
 
   @public
-  val lsuProbe = IO(Output(Probe(new LSUProbe(param))))
-  val probeWire = Wire(new LSUProbe(param))
-  define(lsuProbe, ProbeValue(probeWire))
+  val lsuProbe = IO(Output(Probe(new LSUProbe(param), layers.Verification)))
 
   // read vrf
   val otherTryReadVrf: UInt = Mux(otherUnit.vrfReadDataPorts.valid, otherUnit.status.targetLane, 0.U)
@@ -275,26 +273,31 @@ class LSU(param: LSUParameter) extends Module {
     write.io.enq.bits.data := Mux(otherTryToWrite(index), otherUnit.vrfWritePort.bits, loadUnit.vrfWritePort(index).bits)
     write.io.enq.bits.targetLane := (BigInt(1) << index).U
     loadUnit.vrfWritePort(index).ready := write.io.enq.ready && !otherTryToWrite(index)
+  }
 
-    // probes
-    probeWire.slots(index).dataVd := write.io.enq.bits.data.vd
-    probeWire.slots(index).dataOffset := write.io.enq.bits.data.offset
-    probeWire.slots(index).dataMask := write.io.enq.bits.data.mask
-    probeWire.slots(index).dataData := write.io.enq.bits.data.data
-    probeWire.slots(index).dataInstruction := write.io.enq.bits.data.instructionIndex
-    probeWire.slots(index).writeValid := write.io.enq.valid
-    probeWire.slots(index).targetLane := OHToUInt(write.io.enq.bits.targetLane)
+  layer.block(layers.Verification) {
+    val probeWire = Wire(new LSUProbe(param))
+    define(lsuProbe, ProbeValue(probeWire))
+    writeQueueVec.zipWithIndex.foreach { case (write, index) =>
+      probeWire.slots(index).dataVd := write.io.enq.bits.data.vd
+      probeWire.slots(index).dataOffset := write.io.enq.bits.data.offset
+      probeWire.slots(index).dataMask := write.io.enq.bits.data.mask
+      probeWire.slots(index).dataData := write.io.enq.bits.data.data
+      probeWire.slots(index).dataInstruction := write.io.enq.bits.data.instructionIndex
+      probeWire.slots(index).writeValid := write.io.enq.valid
+      probeWire.slots(index).targetLane := OHToUInt(write.io.enq.bits.targetLane)
+    }
+    probeWire.reqEnq := reqEnq.asUInt
+
+    probeWire.storeUnitProbe := probe.read(storeUnit.probe)
+    probeWire.otherUnitProbe := probe.read(otherUnit.probe)
+    probeWire.lsuInstructionValid :=
+      // The load unit becomes idle when it writes vrf for the last time.
+      maskAnd(!loadUnit.status.idle || VecInit(loadUnit.vrfWritePort.map(_.valid)).asUInt.orR,
+        indexToOH(loadUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt |
+        maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt |
+        maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt
   }
-  probeWire.reqEnq := reqEnq.asUInt
-
-  probeWire.storeUnitProbe := probe.read(storeUnit.probe)
-  probeWire.otherUnitProbe := probe.read(otherUnit.probe)
-  probeWire.lsuInstructionValid :=
-    // The load unit becomes idle when it writes vrf for the last time.
-    maskAnd(!loadUnit.status.idle || VecInit(loadUnit.vrfWritePort.map(_.valid)).asUInt.orR,
-      indexToOH(loadUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt |
-      maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt |
-      maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt
 
   vrfWritePort.zip(writeQueueVec).foreach { case (p, q) =>
     p.valid := q.io.deq.valid

t1/src/lsu/LoadUnit.scala

@@ -217,28 +217,23 @@ class LoadUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
     */
   // Load Unit ready to accpet LSU request
   @public
-  val lsuRequestValidProbe = IO(Output(Probe(Bool())))
-  define(lsuRequestValidProbe, ProbeValue(lsuRequest.valid))
+  val lsuRequestValidProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   // Load Unit is idle
   @public
-  val idleProbe = IO(Output(Probe(Bool())))
-  define(idleProbe, ProbeValue(status.idle))
+  val idleProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   // Tilelink Channel A decouple IO status
   // ready: channel A is ready to accept signal
   // valid: Load Unit try to send signal to channel A
   @public
-  val tlPortAValidProbe = IO(Output(Probe(Bool())))
-  define(tlPortAValidProbe, ProbeValue(memRequest.valid))
+  val tlPortAValidProbe = IO(Output(Probe(Bool(), layers.Verification)))
   @public
-  val tlPortAReadyProbe = IO(Output(Probe(Bool())))
-  define(tlPortAReadyProbe, ProbeValue(memRequest.ready))
+  val tlPortAReadyProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   // Fail to send signal to tilelink Channel A because of address conflict
   @public
-  val addressConflictProbe = IO(Output(Probe(Bool())))
-  define(addressConflictProbe, ProbeValue(addressConflict))
+  val addressConflictProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   //  // Tilelink used for accepting signal from receive signal from Channel D
   //  @public
@@ -285,37 +280,52 @@ class LoadUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
   // After receiving new cacheline from top, or current item is the last cacheline,
   // pop out data and transform it to an aligned cacheline, go through alignedDequeue to next level
   @public
-  val unalignedCacheLineProbe = IO(Output(Probe(Bool())))
-  define(unalignedCacheLineProbe, ProbeValue(unalignedCacheLine.valid))
+  val unalignedCacheLineProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   // Used for transmitting data from unalignedCacheline to dataBuffer
   @public
-  val alignedDequeueValidProbe = IO(Output(Probe(Bool())))
-  define(alignedDequeueValidProbe, ProbeValue(alignedDequeue.valid))
+  val alignedDequeueValidProbe = IO(Output(Probe(Bool(), layers.Verification)))
+
   @public
-  val alignedDequeueReadyProbe = IO(Output(Probe(Bool())))
-  define(alignedDequeueReadyProbe, ProbeValue(alignedDequeue.ready))
+  val alignedDequeueReadyProbe = IO(Output(Probe(Bool(), layers.Verification)))
 
   @public
-  val bufferEnqueueSelectProbe = IO(Output(Probe(chiselTypeOf(bufferEnqueueSelect))))
-  define(bufferEnqueueSelectProbe, ProbeValue(bufferEnqueueSelect))
+  val bufferEnqueueSelectProbe = IO(Output(Probe(chiselTypeOf(bufferEnqueueSelect), layers.Verification)))
 
   // Load Unit can write VRF after writeReadyForLSU is true
   @public
-  val writeReadyForLSUProbe: Bool = IO(Output(Probe(chiselTypeOf(writeReadyForLsu))))
-  define(writeReadyForLSUProbe, ProbeValue(writeReadyForLsu))
+  val writeReadyForLSUProbe: Bool = IO(Output(Probe(chiselTypeOf(writeReadyForLsu), layers.Verification)))
+
 
   // Write to VRF
   @public
   val vrfWriteValidProbe: Seq[Bool] = vrfWritePort.map(port => {
-    val probe = IO(Output(Probe(Bool())))
-    define(probe, ProbeValue(port.valid))
+    val probe = IO(Output(Probe(Bool(), layers.Verification)))
+    layer.block(layers.Verification) {
+      define(probe, ProbeValue(port.valid))
+    }
     probe
-  }).toSeq
+  })
   @public
   val vrfWriteReadyProbe: Seq[Bool] = vrfWritePort.map(port => {
-    val probe = IO(Output(Probe(Bool())))
-    define(probe, ProbeValue(port.ready))
+    val probe = IO(Output(Probe(Bool(), layers.Verification)))
+    layer.block(layers.Verification) {
+      define(probe, ProbeValue(port.ready))
+      }
     probe
   }).toSeq
+
+  layer.block(layers.Verification) {
+    define(lsuRequestValidProbe, ProbeValue(lsuRequest.valid))
+    define(idleProbe, ProbeValue(status.idle))
+    define(tlPortAValidProbe, ProbeValue(memRequest.valid))
+    define(tlPortAReadyProbe, ProbeValue(memRequest.ready))
+    define(addressConflictProbe, ProbeValue(addressConflict))
+    define(unalignedCacheLineProbe, ProbeValue(unalignedCacheLine.valid))
+    define(alignedDequeueValidProbe, ProbeValue(alignedDequeue.valid))
+    define(alignedDequeueReadyProbe, ProbeValue(alignedDequeue.ready))
+    define(bufferEnqueueSelectProbe, ProbeValue(bufferEnqueueSelect))
+    define(writeReadyForLSUProbe, ProbeValue(writeReadyForLsu))
+  }
+
 }