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chipsalliance / t1 Public

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[rocketv] Debug the rocket-v with s-mode registers#720

Merged

sequencer merged 5 commits intochipsalliance:real-rocket-vchipsalliance/t1:real-rocket-vfrom PorterLu:real-rocket-v-sPorterLu/t1:real-rocket-v-sCopy head branch name to clipboard

Aug 14, 2024

+69-58

Conversation Commits5 (5)Checks Files changed

Commits

Commits on Aug 13, 2024

[rocketemu] fix isa parser
PorterLu
committed
[rocketv] add smrnmi and s
PorterLu
committed
[rocketv] replace the CustomCSR with standard CSR
PorterLu
committed
[rocketv] set usingSupervisor and usingNMI according to config
PorterLu
committed
[rocketemu] reset nmi
PorterLu
committed

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