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[rocketv] Elaborate RocketChip with MSU privilege #710

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merged 3 commits into from
Aug 10, 2024
Merged

[rocketv] Elaborate RocketChip with MSU privilege #710

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42ac732
[rocketv] only FIOM is writable currently
PorterLu Aug 8, 2024
25572c3
add msu config
PorterLu Aug 9, 2024
3f5cfc7
fix connection in RocketTileInterface
PorterLu Aug 9, 2024
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1 change: 1 addition & 0 deletions rocketemu/src/TestBench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ class TestBench(generator: SerializableModuleGenerator[RocketTile, RocketTilePar
dut.io.mtip := 0.U
dut.io.meip := 0.U
dut.io.msip := 0.U
dut.io.seip.foreach(_ := 0.U)
dut.io.buserror := 0.U

// get resetVector from simulator
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70 changes: 70 additions & 0 deletions rocketv/configs/james.json
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@@ -0,0 +1,70 @@
{
"parameter": {
"useAsyncReset": false,
"clockGate": true,
"instructionSets": ["rv32_i"],
"priv": "msu",
"hartIdLen": 4,
"useBPWatch": false,
"mcontextWidth": 0,
"scontextWidth": 0,
"asidBits": 0,
"resetVectorBits": 32,
"nBreakpoints": 0,
"dtlbNWays": 32,
"dtlbNSets": 64,
"itlbNSets": 64,
"itlbNWays": 32,
"itlbNSectors": 4,
"itlbNSuperpageEntries": 4,
"nPTECacheEntries": 0,
"nL2TLBWays": 1,
"nL2TLBEntries": 0,
"paddrBits": 32,
"cacheBlockBytes": 32,
"nPMPs": 8,
"legal": "b????????????????????????????????",
"cacheable": "b1???????????????????????????????",
"read": "b????????????????????????????????",
"write": "b????????????????????????????????",
"putPartial": "b????????????????????????????????",
"logic": "b0",
"arithmetic": "b0",
"exec": "b1???????????????????????????????",
"sideEffects": "b00??????????????????????????????",
"btbEntries": 28,
"btbNMatchBits": 14,
"btbUpdatesOutOfOrder": false,
"nPages": 6,
"nRAS": 6,
"bhtParameter": [
{
"nEntries": 512,
"counterLength": 1,
"historyLength": 8,
"historyBits": 3
}
],
"mulDivLatency": 2,
"divUnroll": 1,
"divEarlyOut": false,
"divEarlyOutGranularity": 0,
"mulUnroll": 1,
"mulEarlyOut": false,
"sfmaLatency": 3,
"dfmaLatency": 3,
"divSqrt": true,
"flushOnFenceI": true,
"fastLoadByte": false,
"fastLoadWord": false,
"dcacheNSets": 64,
"dcacheNWays": 4,
"dcacheRowBits": 32,
"maxUncachedInFlight": 1,
"separateUncachedResp": false,
"iCacheNSets": 32,
"iCacheNWays": 4,
"iCachePrefetch": false
},
"generator": "org.chipsalliance.rocketv.RocketTile"
}
8 changes: 4 additions & 4 deletions rocketv/src/CSR.scala
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Expand Up @@ -368,7 +368,7 @@ class CSR(val parameter: CSRParameter)
case (32, 2) => 1
case (64, x) if x >= 3 && x <= 6 => x + 5
}
def write(fiom: Envcfg, wdata: UInt) {
def write(fiom: Bool, wdata: UInt) {
val new_envcfg = wdata.asTypeOf(new Envcfg)
fiom := new_envcfg.fiom // only FIOM is writable currently
}
Expand Down Expand Up @@ -1528,7 +1528,7 @@ class CSR(val parameter: CSRParameter)
when(decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
when(decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
when(decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
when(decoded_addr(CSRs.senvcfg)) { write(reg_senvcfg, wdata) }
when(decoded_addr(CSRs.senvcfg)) { write(reg_senvcfg.fiom, wdata) }
}

if (usingHypervisor) {
Expand Down Expand Up @@ -1603,11 +1603,11 @@ class CSR(val parameter: CSRParameter)
when(decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
when(decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
when(decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
when(decoded_addr(CSRs.henvcfg)) { write(reg_henvcfg, wdata) }
when(decoded_addr(CSRs.henvcfg)) { write(reg_henvcfg.fiom, wdata) }
}
if (usingUser) {
when(decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
when(decoded_addr(CSRs.menvcfg)) { write(reg_menvcfg, wdata) }
when(decoded_addr(CSRs.menvcfg)) { write(reg_menvcfg.fiom, wdata) }
}
if (nBreakpoints > 0) {
when(decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
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10 changes: 5 additions & 5 deletions rocketv/src/RocketTile.scala
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Expand Up @@ -375,11 +375,11 @@ class RocketTileInterface(parameter: RocketTileParameter) extends Bundle {
val mtip: Bool = Input(Bool())
val msip: Bool = Input(Bool())
val meip: Bool = Input(Bool())
val seip: Option[Bool] = Option.when(parameter.usingSupervisor)(Bool())
val lip: Vec[Bool] = Vec(parameter.nLocalInterrupts, Bool())
val nmi = Option.when(parameter.usingNMI)(Bool())
val nmiInterruptVector = Option.when(parameter.usingNMI)(UInt(parameter.resetVectorBits.W))
val nmiIxceptionVector = Option.when(parameter.usingNMI)(UInt(parameter.resetVectorBits.W))
val seip: Option[Bool] = Option.when(parameter.usingSupervisor)(Input(Bool()))
val lip: Vec[Bool] = Input(Vec(parameter.nLocalInterrupts, Bool()))
val nmi = Option.when(parameter.usingNMI)(Input(Bool()))
val nmiInterruptVector = Option.when(parameter.usingNMI)(Input(UInt(parameter.resetVectorBits.W)))
val nmiIxceptionVector = Option.when(parameter.usingNMI)(Input(UInt(parameter.resetVectorBits.W)))
// TODO: buserror should be handled by NMI
val buserror: Bool = Input(Bool())
val wfi: Bool = Output(Bool())
Expand Down