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[rtl] Remove empty write. #681

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merged 2 commits into from
Jul 22, 2024
+29 −29
Merged

[rtl] Remove empty write. #681

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b83d25b
[rtl] Remove empty write.
qinjun-li Jul 22, 2024
76f0cae
[ci] update test case cycle data
invalid-email-address Jul 22, 2024
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18 changes: 9 additions & 9 deletions .github/cases/blastoise/default.json
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Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
"mlir.stripmining": 26736,
"asm.mmm": 92573,
"asm.smoke": 4867,
"intrinsic.conv2d_less_m2": 2612,
"intrinsic.conv2d_less_m2": 2594,
"intrinsic.linear_normalization": 3280,
"intrinsic.softmax": 8348,
"intrinsic.softmax": 8347,
"codegen.vaadd_vv": 91859,
"codegen.vaadd_vx": 253663,
"codegen.vaaddu_vv": 91859,
Expand Down Expand Up @@ -499,14 +499,14 @@
"codegen.vfredusum_vs": 122275,
"codegen.vfredmax_vs": 122275,
"codegen.vfredmin_vs": 122275,
"rvv_bench.ascii_to_utf16": 1583921,
"rvv_bench.ascii_to_utf32": 704111,
"rvv_bench.byteswap": 3353234,
"rvv_bench.ascii_to_utf16": 1583663,
"rvv_bench.ascii_to_utf32": 703954,
"rvv_bench.byteswap": 3353148,
"rvv_bench.chacha20": 2,
"rvv_bench.mandelbrot": 4056018,
"rvv_bench.memcpy": 2152069,
"rvv_bench.memset": 439171,
"rvv_bench.mergelines": 3338064,
"rvv_bench.mandelbrot": 4055961,
"rvv_bench.memcpy": 2131904,
"rvv_bench.memset": 438545,
"rvv_bench.mergelines": 3337870,
"rvv_bench.poly1305": 2,
"rvv_bench.strlen": 877539,
"rvv_bench.utf8_count": 6340756
Expand Down
14 changes: 7 additions & 7 deletions .github/cases/machamp/default.json
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
"mlir.stripmining": 13425,
"asm.mmm": 91428,
"asm.smoke": 5005,
"intrinsic.conv2d_less_m2": 2612,
"intrinsic.conv2d_less_m2": 2585,
"codegen.vaadd_vv": 90595,
"codegen.vaadd_vx": 250851,
"codegen.vaaddu_vv": 90595,
Expand Down Expand Up @@ -435,13 +435,13 @@
"codegen.vxor_vx": 63090,
"codegen.vzext_vf2": 39398,
"codegen.vzext_vf4": 6420,
"rvv_bench.ascii_to_utf16": 1460381,
"rvv_bench.ascii_to_utf32": 631370,
"rvv_bench.byteswap": 3259113,
"rvv_bench.ascii_to_utf16": 1460078,
"rvv_bench.ascii_to_utf32": 631187,
"rvv_bench.byteswap": 3259002,
"rvv_bench.chacha20": 2,
"rvv_bench.memcpy": 1905444,
"rvv_bench.memset": 244925,
"rvv_bench.mergelines": 3137885,
"rvv_bench.memcpy": 1875713,
"rvv_bench.memset": 244319,
"rvv_bench.mergelines": 3137759,
"rvv_bench.poly1305": 2,
"rvv_bench.strlen": 710421,
"rvv_bench.utf8_count": 5729721
Expand Down
14 changes: 7 additions & 7 deletions .github/cases/sandslash/default.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
"mlir.stripmining": 3577,
"asm.mmm": 91437,
"asm.smoke": 3558,
"intrinsic.conv2d_less_m2": 2612,
"intrinsic.conv2d_less_m2": 2576,
"codegen.vaadd_vv": 119061,
"codegen.vaadd_vx": 336401,
"codegen.vaaddu_vv": 119061,
Expand Down Expand Up @@ -435,13 +435,13 @@
"codegen.vxor_vx": 84837,
"codegen.vzext_vf2": 134873,
"codegen.vzext_vf4": 19800,
"rvv_bench.ascii_to_utf16": 1371886,
"rvv_bench.ascii_to_utf32": 583519,
"rvv_bench.byteswap": 3556432,
"rvv_bench.ascii_to_utf16": 1371550,
"rvv_bench.ascii_to_utf32": 583318,
"rvv_bench.byteswap": 3556315,
"rvv_bench.chacha20": 2,
"rvv_bench.memcpy": 1739436,
"rvv_bench.memset": 131052,
"rvv_bench.mergelines": 3038652,
"rvv_bench.memcpy": 1704869,
"rvv_bench.memset": 130483,
"rvv_bench.mergelines": 3038600,
"rvv_bench.poly1305": 2,
"rvv_bench.strlen": 715272,
"rvv_bench.utf8_count": 4797732
Expand Down
12 changes: 6 additions & 6 deletions t1/src/lsu/StoreUnit.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
val lastDataGroupReg: UInt = RegEnable(lastDataGroupForInstruction, 0.U, lsuRequest.valid)
val nextDataGroup: UInt = Mux(lsuRequest.valid, 0.U, dataGroup + 1.U)
val isLastRead: Bool = dataGroup === lastDataGroupReg
val lastGroupAndNeedAlign: Bool = initOffset.orR && isLastRead

// stage1, 读vrf
// todo: need hazardCheck?
Expand Down Expand Up @@ -159,12 +158,12 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
// 存每条cache 的mask, 也许能优化, 暂时先这样
val maskForBufferData: Vec[UInt] = RegInit(VecInit(Seq.fill(8)(0.U(param.lsuTransposeSize.W))))
val maskForBufferDequeue: UInt = maskForBufferData(cacheLineIndexInBuffer)
val tailLeft2: Bool = RegInit(false.B)
val lastDataGroupInDataBuffer: Bool = RegInit(false.B)
val alignedDequeueFire: Bool = memRequest.fire
// cache 不对齐的时候的上一条残留
val cacheLineTemp: UInt = RegEnable(dataBuffer.head, 0.U((param.lsuTransposeSize * 8).W), alignedDequeueFire)
val maskTemp: UInt = RegInit(0.U(param.lsuTransposeSize.W))
val tailValid: Bool = RegInit(false.B)
val canSendTail: Bool = RegInit(false.B)
val isLastCacheLineInBuffer: Bool = cacheLineIndexInBuffer === lsuRequestReg.instructionInformation.nf
val bufferWillClear: Bool = alignedDequeueFire && isLastCacheLineInBuffer
accessBufferDequeueReady := !bufferValid || (memRequest.ready && isLastCacheLineInBuffer)
Expand All @@ -176,7 +175,7 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
// 把数据regroup, 然后放去 [[dataBuffer]]
when(accessBufferDequeueFire) {
maskForBufferData := cutUInt(fillBySeg, param.lsuTransposeSize)
tailLeft2 := lastGroupAndNeedAlign
lastDataGroupInDataBuffer := isLastRead
// todo: 只是因为参数恰好是一个方形的, 需要写一个反的
dataBuffer := Mux1H(dataEEWOH, Seq.tabulate(3) { sewSize =>
// 每个数据块 2 ** sew byte
Expand Down Expand Up @@ -238,11 +237,12 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {

when(lsuRequest.valid || alignedDequeueFire) {
maskTemp := Mux(lsuRequest.valid, 0.U, maskForBufferDequeue)
tailValid := Mux(lsuRequest.valid, false.B, bufferValid && tailLeft2 && isLastCacheLineInBuffer)
canSendTail := !lsuRequest.valid && bufferValid && isLastCacheLineInBuffer && lastDataGroupInDataBuffer
}

// 连接 alignedDequeue
memRequest.valid := bufferValid || tailValid
val needSendTail: Bool = bufferBaseCacheLineIndex === cacheLineNumberReg
memRequest.valid := bufferValid || (canSendTail && needSendTail)
// aligned
memRequest.bits.data :=
multiShifter(right = false, multiSize = 8)(dataBuffer.head ## cacheLineTemp, initOffset) >> cacheLineTemp.getWidth
Expand Down