[script] remove old case dir index logic

.github/workflows/pr.yml

@@ -185,12 +185,8 @@ jobs:
           mv "$waveFile" ./wave-${{ matrix.job }}.fst
       - uses: actions/upload-artifact@v4
         with:
-          name: failed-tests-wave-${{ matrix.id }}
+          name: ${{ matrix.id }}-failed-tests-wave
           path: 'wave-*.fst'
-      - run: |
-          echo "Test ${{ matrix.job }} run fail"
-          # We are just running post action for failing test, so we need to avoid the workflow finishing successfully
-          exit 1
 
   report:
     name: "Report CI result"

scripts/run-test.py

@@ -53,15 +53,6 @@ def main():
             default=None,
             help="path to the subsystem emulator, use nix generated one if unspecified",
         )
-        subparser.add_argument(
-            "--cases-dir",
-            help="path to testcases, default to TEST_CASES_DIR environment",
-        )
-        subparser.add_argument(
-            "--use-individual-drv",
-            help="use .#t1.cases.<case_type>.<case_name> instead of .#t1.cases.all",
-            action="store_true",
-        )
         subparser.add_argument(
             "--force-x86",
             help="use cases built in x86, for non-x86 machines not capable of building cases",
@@ -154,34 +145,23 @@ def main():
 
 
 # Try to search ELF from the given directory
-def load_elf_from_dir(config, cases_dir, case_name, use_individual_drv, force_x86):
+def load_elf_from_dir(config, case_name, force_x86):
     cases_attr_name = "cases-x86" if force_x86 else "cases"
-    if cases_dir is None:
-        if env_case_dir := os.environ.get("TEST_CASES_DIR"):
-            cases_dir = env_case_dir
-        else:
-            nix_args = [
-                "nix",
-                "build",
-                "--no-link",
-                "--print-out-paths",
-                "--no-warn-dirty",
-            ]
-            if use_individual_drv:
-                nix_args.append(f".#t1.{cases_attr_name}.{case_name}")
-            else:
-                nix_args.append(f".#t1.{config}.{cases_attr_name}.all")
-            logger.info(f'Run "{" ".join(nix_args)}"')
-            cases_dir = subprocess.check_output(nix_args).strip().decode("UTF-8")
+    nix_args = [
+        "nix",
+        "build",
+        "--no-link",
+        "--print-out-paths",
+        "--no-warn-dirty",
+    ]
+    nix_args.append(f".#t1.{config}.{cases_attr_name}.{case_name}")
+    logger.info(f'Run "{" ".join(nix_args)}"')
+    cases_dir = subprocess.check_output(nix_args).strip().decode("UTF-8")
 
     cases_dir = Path(cases_dir)
     logger.info(f"Running cases in {cases_dir}")
 
-    case_config_path = (
-        cases_dir / f"{case_name}.json"
-        if use_individual_drv
-        else cases_dir / "configs" / f"{case_name}.json"
-    )
+    case_config_path = cases_dir / f"{case_name}.json"
     assert case_config_path.exists(), f"cannot find case config in {case_config_path}"
     config = json.loads(case_config_path.read_text())
 
@@ -216,9 +196,7 @@ def run_test(args):
         if Path(args.case).exists()
         else load_elf_from_dir(
             args.config,
-            args.cases_dir,
             args.case,
-            args.use_individual_drv,
             args.force_x86,
         )
     )
@@ -253,32 +231,42 @@ def optionals(cond, items):
         dramsim3_cfg = args.dramsim3_cfg
         rtl_config = json.loads(elaborate_config_path.read_text())
         tck = 10**3 / args.frequency
-        emu_args = [
-            "--elf", str(case_elf_path),
-            "--wave", str(Path(args.out_dir) / "wave.fst"),
-            "--timeout", str(args.cosim_timeout),
-            "--tck", str(tck),
-            "--perf", str(Path(args.out_dir) / "perf.txt"),
-            "--vlen", str(rtl_config["parameter"]["vLen"]),
-            "--dlen", str(rtl_config["parameter"]["dLen"]),
-            # TODO: this will be refactored soon to support multiple LSU
-            "--tl_bank_number", str(rtl_config["parameter"]["lsuInstantiateParameters"][0]["banks"])
-        ] + optionals(args.no_logging, [
-              "--no-logging"
-            ]) \
-          + optionals(not args.with_file_logging,[
-              "--no-file-logging"
-            ]) \
-          + optionals(args.no_console_logging, [
-              "--no-console-logging"
-            ]) \
-          + optionals(args.out_dir, [
-              f"--log-path={str(Path(args.out_dir) / 'emulator.log')}"
-            ]) \
-          + optionals(dramsim3_cfg is not None, [
-              "--dramsim3-result", str(Path(args.out_dir) / "dramsim3-logs"),
-              "--dramsim3-config", dramsim3_cfg,
-            ])
+        emu_args = (
+            [
+                "--elf",
+                str(case_elf_path),
+                "--wave",
+                str(Path(args.out_dir) / "wave.fst"),
+                "--timeout",
+                str(args.cosim_timeout),
+                "--tck",
+                str(tck),
+                "--perf",
+                str(Path(args.out_dir) / "perf.txt"),
+                "--vlen",
+                str(rtl_config["parameter"]["vLen"]),
+                "--dlen",
+                str(rtl_config["parameter"]["dLen"]),
+                # TODO: this will be refactored soon to support multiple LSU
+                "--tl_bank_number",
+                str(rtl_config["parameter"]["lsuInstantiateParameters"][0]["banks"]),
+            ]
+            + optionals(args.no_logging, ["--no-logging"])
+            + optionals(not args.with_file_logging, ["--no-file-logging"])
+            + optionals(args.no_console_logging, ["--no-console-logging"])
+            + optionals(
+                args.out_dir, [f"--log-path={str(Path(args.out_dir) / 'emulator.log')}"]
+            )
+            + optionals(
+                dramsim3_cfg is not None,
+                [
+                    "--dramsim3-result",
+                    str(Path(args.out_dir) / "dramsim3-logs"),
+                    "--dramsim3-config",
+                    dramsim3_cfg,
+                ],
+            )
+        )
 
     elif emu_type == "subsystem":
         emu_args = [f"+init_file={case_elf_path}"]

tests/mlir/axpy_masked/axpy_masked.mlir

@@ -0,0 +1,53 @@
+#map0 = affine_map<(d0) -> (d0)>
+#map1 = affine_map<(d0) -> (d0 ceildiv 64)>
+
+memref.global "private" @gv_i32 : memref<4100xi32> // 4100 = 128 * 32 + 4
+
+func.func @test() -> i32 {
+
+  %input1 = memref.get_global @gv_i32 : memref<4100xi32>
+
+  %input2 = memref.get_global @gv_i32 : memref<4100xi32>
+  %output = memref.get_global @gv_i32 : memref<4100xi32>
+
+  %c0 = arith.constant 0 : index
+  %c0_i32 = arith.constant 0 : i32
+  %c0_vector = arith.constant dense<0> : vector<64xi32>
+  %c64 = arith.constant 64 : index
+  %dim = memref.dim %input1, %c0 : memref<4100xi32>
+
+  %a_vector = affine.vector_load %input1[%c0] : memref<4100xi32>, vector<64xi32>
+
+  affine.for %idx = #map0(%c0) to #map1(%dim) {
+    %curlen = arith.muli %idx, %c64 : index
+    %remain = arith.subi %dim, %curlen : index
+    %cmp = arith.cmpi sge, %remain, %c64 : index
+    scf.if %cmp {
+      %x_vector = affine.vector_load %input1[%idx * 64] : memref<4100xi32>, vector<64xi32>
+      %y_vector = affine.vector_load %input2[%idx * 64] : memref<4100xi32>, vector<64xi32>
+      %mul_vector = arith.muli %x_vector, %a_vector : vector<64xi32>
+      %result_vector = arith.addi %mul_vector, %y_vector : vector<64xi32>
+      affine.vector_store %result_vector, %output[%idx * 64] : memref<4100xi32>, vector<64xi32>
+    } else {
+      // TODO: `vector.create_mask` operation will result in the error "spike trapped with trap_illegal_instruction", which needs further analysis.
+      // %mask64 = vector.create_mask %remain : vector<64xi1>
+      %mask64 = arith.constant dense<1> : vector<64xi1>
+      %remain_i32 = arith.index_cast %remain : index to i32
+      %x_vector = vector.maskedload %input1[%curlen], %mask64, %c0_vector : memref<4100xi32>, vector<64xi1>, vector<64xi32> into vector<64xi32>
+      %y_vector = vector.maskedload %input2[%curlen], %mask64, %c0_vector : memref<4100xi32>, vector<64xi1>, vector<64xi32> into vector<64xi32>
+      %mul_vector = arith.muli %x_vector, %a_vector : vector<64xi32>
+      %result_vector = arith.addi %mul_vector, %y_vector : vector<64xi32>
+      vector.maskedstore %output[%curlen], %mask64, %result_vector : memref<4100xi32>, vector<64xi1>, vector<64xi32>
+    }
+  }
+
+  %result = vector.load %output[%c0] : memref<4100xi32>, vector<8xi32>
+
+  %mask_res = arith.constant dense<1> : vector<8xi1>
+  %c1_i32 = arith.constant 1 : i32
+  %evl = arith.constant 8 : i32
+  %res_reduce_add_mask_driven = "llvm.intr.vp.reduce.add" (%c1_i32, %result, %mask_res, %evl) :
+        (i32, vector<8xi32>, vector<8xi1>, i32) -> i32
+
+  return %res_reduce_add_mask_driven : i32
+}

tests/mlir/axpy_masked/default.nix

@@ -1,7 +1,7 @@
 { testcase-env }:
 testcase-env.mkMlirCase {
   caseName = "axpy_masked";
-  src = ./axpy-masked.mlir;
+  src = ./axpy_masked.mlir;
   linkSrcs = [
     ../main.S
   ];

tests/mlir/maxvl_tail_setvl_front/default.nix

@@ -1,7 +1,7 @@
 { testcase-env }:
 testcase-env.mkMlirCase {
   caseName = "maxvl_tail_setvl_front";
-  src = ./maxvl-tail-setvl-front.mlir;
+  src = ./maxvl_tail_setvl_front.mlir;
   linkSrcs = [
     ../main.S
   ];

tests/mlir/maxvl_tail_setvl_front/maxvl_tail_setvl_front.mlir

@@ -0,0 +1,56 @@
+memref.global "private" @input_A : memref<1500xi32>
+memref.global "private" @input_B : memref<1500xi32>
+memref.global "private" @output : memref<1500xi32>
+
+#map_1 = affine_map<(d)[B, N] -> (N*d + B)>
+
+func.func @test() -> i32 {
+  // for (i = 0; i < n; i++) C[i] = A[i] + B[i]
+  // use MAXVL as a fix vector length
+  // use setvl to do tail-processing
+  %A = memref.get_global @input_A : memref<1500xi32>
+  %B = memref.get_global @input_B : memref<1500xi32>
+  %C = memref.get_global @output : memref<1500xi32>
+  %n = arith.constant 1500 : i32
+
+  // just need 2 vec-reg, use SEV=32, LMUL=8
+  // e32 = 0b010, m8 = 0b011, vscale = [16] 
+  %sew = arith.constant 2 : i32
+  %lmul = arith.constant 3 : i32
+  %maxvl = "rvv.setvl"(%n, %sew, %lmul) : (i32, i32, i32) -> i32
+  %maxvl_idx = arith.index_cast %maxvl : i32 to index
+
+
+  %iter_end = arith.divui %n, %maxvl : i32
+  %rem = arith.remui %n, %maxvl : i32
+
+  %c0 = arith.constant 0 : i32
+  %c0_idx = arith.constant 0 : index
+
+  %tail = arith.cmpi ne, %rem, %c0 : i32
+  scf.if %tail {
+    %new_vl = "rvv.setvl"(%rem, %sew, %lmul) : (i32, i32, i32) -> i32
+
+    %A_vec = "rvv.load"(%A, %c0_idx, %new_vl) : (memref<1500xi32>, index, i32) -> vector<[16]xi32>
+    %B_vec = "rvv.load"(%B, %c0_idx, %new_vl) : (memref<1500xi32>, index, i32) -> vector<[16]xi32>
+    %sum = "rvv.add"(%A_vec, %B_vec, %new_vl) : (vector<[16]xi32>, vector<[16]xi32>, i32) -> vector<[16]xi32>
+    "rvv.store"(%sum, %C, %c0_idx, %new_vl) : (vector<[16]xi32>, memref<1500xi32>, index, i32) -> ()
+  }
+
+  %new_maxvl = "rvv.setvl"(%n, %sew, %lmul) : (i32, i32, i32) -> i32
+  %new_maxvl_idx = arith.index_cast %new_maxvl : i32 to index
+  %iter_end_idx = arith.index_cast %iter_end : i32 to index
+  %rem_idx = arith.index_cast %rem : i32 to index
+  affine.for %i_ = 0 to %iter_end_idx step 1 {
+    // i = REM + i_ * MAXVL, this make loop for i_ be a normalized loop 
+    %i = affine.apply #map_1(%i_)[%rem_idx, %new_maxvl_idx]
+
+    %A_vec = "rvv.load"(%A, %i, %new_maxvl) : (memref<1500xi32>, index, i32) -> vector<[16]xi32>
+    %B_vec = "rvv.load"(%B, %i, %new_maxvl) : (memref<1500xi32>, index, i32) -> vector<[16]xi32>
+    %sum = "rvv.add"(%A_vec, %B_vec, %new_maxvl) : (vector<[16]xi32>, vector<[16]xi32>, i32) -> vector<[16]xi32>
+    "rvv.store"(%sum, %C, %i, %new_maxvl) : (vector<[16]xi32>, memref<1500xi32>, index, i32) -> ()
+  }
+
+  %ret = arith.constant 0 : i32
+  return %ret : i32
+}

tests/mlir/rvv_vp_intrinsic_add/default.nix

@@ -1,7 +1,7 @@
 { testcase-env }:
 testcase-env.mkMlirCase {
   caseName = "rvv_vp_intrinsic_add";
-  src = ./rvv-vp-intrinsic-add.mlir;
+  src = ./rvv_vp_intrinsic_add.mlir;
   linkSrcs = [
     ../main.S
   ];

tests/mlir/rvv_vp_intrinsic_add/rvv_vp_intrinsic_add.mlir

@@ -0,0 +1,64 @@
+// This implementation is based on [this file](https://github.com/buddy-compiler/buddy-mlir/blob/main/examples/RVVExperiment/rvv-vp-intrinsic-add.mlir) from buddy-mlir.
+
+memref.global "private" @gv_i32 : memref<20xi32> = dense<[0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+                                                          10, 11, 12, 13, 14, 15, 16, 17, 18, 19]>
+func.func @test() -> i32 {
+  %mem_i32 = memref.get_global @gv_i32 : memref<20xi32>
+  %c0 = arith.constant 0 : index
+  %c1 = arith.constant 1 : index
+  %c1_i32 = arith.constant 1 : i32
+  %mask14 = arith.constant dense<[1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0]> : vector<16xi1>
+  %mask16 = arith.constant dense<1> : vector<16xi1>
+  %evl14 = arith.constant 14 : i32
+  %evl16 = arith.constant 16 : i32
+
+  %mask = arith.constant dense<1> : vector<16xi1>
+  %evl = arith.constant 16 : i32
+  %output0 = arith.constant 0 : i32
+
+  //===---------------------------------------------------------------------------===//
+  // Case 1: VP Intrinsic Add Operation + Fixed Vector Type + Mask Driven
+  //===---------------------------------------------------------------------------===//
+
+  %vec1 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %vec2 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %res_add_mask_driven = "llvm.intr.vp.add" (%vec2, %vec1, %mask14, %evl16) :
+         (vector<16xi32>, vector<16xi32>, vector<16xi1>, i32) -> vector<16xi32>
+
+  %res_add_mask_driven_reduce_add = "llvm.intr.vp.reduce.add" (%c1_i32, %res_add_mask_driven, %mask, %evl) :
+        (i32, vector<16xi32>, vector<16xi1>, i32) -> i32
+  %output1 = arith.addi %output0, %res_add_mask_driven_reduce_add : i32
+
+  //===---------------------------------------------------------------------------===//
+  // Case 2: VP Intrinsic Add Operation + Fixed Vector Type + EVL Driven
+  //===---------------------------------------------------------------------------===//
+
+  %vec3 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %vec4 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %res_add_evl_driven = "llvm.intr.vp.add" (%vec4, %vec3, %mask16, %evl14) :
+         (vector<16xi32>, vector<16xi32>, vector<16xi1>, i32) -> vector<16xi32>
+
+  %res_add_evl_driven_reduce_add = "llvm.intr.vp.reduce.add" (%c1_i32, %res_add_evl_driven, %mask, %evl) :
+        (i32, vector<16xi32>, vector<16xi1>, i32) -> i32
+  %output2 = arith.addi %output1, %res_add_evl_driven_reduce_add : i32
+
+  //===---------------------------------------------------------------------------===//
+  // Case 3: VP Intrinsic Reduce Add Operation + Fixed Vector Type + Mask Driven
+  //===---------------------------------------------------------------------------===//
+
+  %vec9 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %res_reduce_add_mask_driven = "llvm.intr.vp.reduce.add" (%c1_i32, %vec9, %mask14, %evl16) :
+         (i32, vector<16xi32>, vector<16xi1>, i32) -> i32
+  %output3 = arith.addi %output2, %res_reduce_add_mask_driven : i32
+
+  //===---------------------------------------------------------------------------===//
+  // Case 4: VP Intrinsic Reduce Add Operation + Fixed Vector Type + EVL Driven
+  //===---------------------------------------------------------------------------===//
+
+  %vec10 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<16xi32>
+  %res_reduce_add_evl_driven = "llvm.intr.vp.reduce.add" (%c1_i32, %vec10, %mask16, %evl14) :
+         (i32, vector<16xi32>, vector<16xi1>, i32) -> i32
+  %output4 = arith.addi %output3, %res_reduce_add_evl_driven : i32
+
+  return %output4 : i32
+}

tests/mlir/rvv_vp_intrinsic_add_scalable/default.nix

@@ -1,7 +1,7 @@
 { testcase-env }:
 testcase-env.mkMlirCase {
   caseName = "rvv_vp_intrinsic_add_scalable";
-  src = ./rvv-vp-intrinsic-add-scalable.mlir;
+  src = ./rvv_vp_intrinsic_add_scalable.mlir;
   linkSrcs = [
     ../main.S
   ];