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[emulator] rewrite probes to latest perf model #334

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merged 8 commits into from
Nov 1, 2023
+1,068 −1,412
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[emulator] rewrite probes to latest perf model #334

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5cb1c45
[emulator] improve emulator logging performance
Avimitin Oct 26, 2023
8f0d05a
[emulator] rewrite LoadUnit probes to latest perf model
Avimitin Oct 29, 2023
d2f0c94
[emulator] rewrite StoreUnit probes to latest perf model
Avimitin Oct 30, 2023
cf378e7
[emulator] rewrite V top probes to lastest perf model
Avimitin Oct 30, 2023
3265f93
[emulator] rewrite SimpleAccess unit to latest perf model
Avimitin Oct 30, 2023
10ffffe
[emulator] rewrite Lane probes to latest perf model
Avimitin Oct 30, 2023
63025a8
[emulator] rewrite Lane Slots probes to latest perf model
Avimitin Oct 30, 2023
ec23609
[emulator] fix up the emulator log readability
Avimitin Nov 1, 2023
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236 changes: 113 additions & 123 deletions elaborator/src/PerfMonitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,167 +9,157 @@ abstract class PerfMonitor extends DPIModule {
override val trigger: String = s"always @(posedge ${clock.name})";
}

trait IndexedPerfMonitor extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
}

trait ValidMonitor extends PerfMonitor {
val isValid = dpiIn("isValid", Input(Bool()))
}

trait ReadyMonitor extends PerfMonitor {
val isReady = dpiIn("isReady", Input(Bool()))
}


/**
* Monitor signals in [[v.LoadUnit]]
* Monitor signals in [[v.LoadUnit]] [[v.StoreUnit]]
*/
class LoadUnitMonitor extends PerfMonitor {
val tlPortAIsValid = dpiIn("LoadUnitTlPortAIsValid", Input(Bool()))
val tlPortAIsReady = dpiIn("LoadUnitTlPortAIsReady", Input(Bool()))
case class LSUParam(memoryBankSize: Int, laneNumber: Int)

val statusIdle = dpiIn("LoadUnitStatusIdle", Input(Bool()))
class LoadUnitMonitor(param: LSUParam) extends PerfMonitor {
val lsuRequestValid = dpiIn("LSURequestValid", Input(Bool()))

val writeReadyForLSU = dpiIn("LoadUnitWriteReadyForLSU", Input(Bool()))
}
val statusIdle = dpiIn("idle", Input(Bool()))

class LoadUnitPortDMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
val tlPortAIsValid = dpiIn("tlPortAIsValid", Input(Bool()))
val tlPortAIsReady = dpiIn("tlPortAIsReady", Input(Bool()))

class LoadUnitVrfWritePortMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
val addressConflict = dpiIn("addressConflict", Input(Bool()))

class LoadUnitLastCacheLineAckMonitor extends IndexedPerfMonitor {
val isAck = dpiIn("LoadUnitLastCacheLineIsAck", Input(Bool()))
}
val tlPortDIsValid = dpiIn("tlPortDIsValid", Seq.fill(param.memoryBankSize)(Input(Bool())))
val tlPortDIsReady = dpiIn("tlPortDIsReady", Seq.fill(param.memoryBankSize)(Input(Bool())))

class LoadUnitCacheLineDequeueMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
// End of LoadUnit monitor definition
val queueValid = dpiIn("queueValid", Seq.fill(param.memoryBankSize)(Input(Bool())))
val queueReady = dpiIn("queueReady", Seq.fill(param.memoryBankSize)(Input(Bool())))

val cacheLineDequeueValid = dpiIn("cacheLineDequeueValid", Seq.fill(param.memoryBankSize)(Input(Bool())))
val cacheLineDequeueReady = dpiIn("cacheLineDequeueReady", Seq.fill(param.memoryBankSize)(Input(Bool())))

/**
* Monitor signals in [[v.SimpleAccessUnit]]
*/
class OtherUnitMonitor extends PerfMonitor {
val lsuRequestIsValid = dpiIn("SimpleAccessUnitLSURequestIsValid", Input(Bool()))

val vrfReadDataPortsIsReady = dpiIn("SimpleAccessUnitVRFReadDataPortsIsReady", Input(Bool()))
val vrfReadDataPortsIsValid = dpiIn("SimpleAccessUnitVRFReadDataPortsIsValid", Input(Bool()))
val unalignedCacheLine = dpiIn("unalignedCacheLine", Input(Bool()))

val maskSelectIsValid = dpiIn("SimpleAccessUnitMaskSelectIsValid", Input(Bool()))
val alignedDequeueReady = dpiIn("alignedDequeueReady", Input(Bool()))
val alignedDequeueValid = dpiIn("alignedDequeueValid", Input(Bool()))

val vrfWritePortIsReady = dpiIn("SimpleAccessUnitVRFWritePortIsReady", Input(Bool()))
val vrfWritePortIsValid = dpiIn("SimpleAccessUnitVRFWritePortIsValid", Input(Bool()))

val targetLane = dpiIn("SimpleAccessUnitStatusTargetLane", Input(UInt(32.W)))
val idle = dpiIn("SimpleAccessUnitIsIdle", Input(Bool()))
val writeReadyForLSU = dpiIn("LoadUnitWriteReadyForLSU", Input(Bool()))

val s0Fire = dpiIn("SimpleAccessUnitS0Fire", Input(Bool()))
val s1Fire = dpiIn("SimpleAccessUnitS1Fire", Input(Bool()))
val s2Fire = dpiIn("SimpleAccessUnitS2Fire", Input(Bool()))
val vrfWritePortValid = dpiIn("vrfWritePortValid", Seq.fill(param.laneNumber)(Input(Bool())))
val vrfWritePortReady = dpiIn("vrfWritePortReady", Seq.fill(param.laneNumber)(Input(Bool())))
}

class OtherUnitAccessTileLinkMonitor extends ValidMonitor with ReadyMonitor

class OtherUnitTileLinkAckMonitor extends ValidMonitor with ReadyMonitor

class OtherUnitOffsetReadResultMonitor extends IndexedPerfMonitor with ValidMonitor

class OtherUnitIndexedInsnOffsetsIsValidMonitor extends IndexedPerfMonitor with ValidMonitor
// End of SimpleAccessUnit monitors definition
class StoreUnitMonitor(param: LSUParam) extends PerfMonitor {
val idle = dpiIn("idle", Input(Bool()))
val lsuRequestIsValid = dpiIn("lsuRequestIsValid", Input(Bool()))
val tlPortAIsValid = dpiIn("tlPortAIsValid", Seq.fill(param.memoryBankSize)(Input(Bool())))
val tlPortAIsReady = dpiIn("tlPortAIsReady", Seq.fill(param.memoryBankSize)(Input(Bool())))
val addressConflict = dpiIn("addressConflict", Input(Bool()))
val vrfReadDataPortIsValid = dpiIn("vrfReadDataPortIsValid", Seq.fill(param.laneNumber)(Input(Bool())))
val vrfReadDataPortIsReady = dpiIn("vrfReadDataPortIsReady", Seq.fill(param.laneNumber)(Input(Bool())))
val vrfReadyToStore = dpiIn("vrfReadyToStore", Input(Bool()))
val alignedDequeueReady = dpiIn("alignedDequeueReady", Input(Bool()))
val alignedDequeueValid = dpiIn("alignedDequeueValid", Input(Bool()))
}

case class VParam(chainingSize: Int)
class VMonitor(param: VParam) extends PerfMonitor {
val requestValid = dpiIn("requestValid", Input(Bool()))
val requestReady = dpiIn("requestReady", Input(Bool()))

val requestRegValid = dpiIn("requestRegValid", Input(Bool()))

val requestRegDequeueValid = dpiIn("requestRegDequeueValid", Input(Bool()))
val requestRegDequeueReady = dpiIn("requestRegDequeueReady", Input(Bool()))
val executionReady = dpiIn("executionReady", Input(Bool()))
val slotReady = dpiIn("slotReady", Input(Bool()))
val waitForGather = dpiIn("waitForGather", Input(Bool()))
// Can't use 'RAW' here cuz it will be parsed as 'r_a_w' at DPI side
val instructionRawReady = dpiIn("instructionRawReady", Input(Bool()))

val responseValid = dpiIn("responseValid", Input(Bool()))
val sMaskUnitExecuted = dpiIn("sMaskUnitExecuted", Seq.fill(param.chainingSize)(Input(Bool())))
val wLast = dpiIn("wLast", Seq.fill(param.chainingSize)(Input(Bool())))
val isLastInst = dpiIn("isLastInst", Seq.fill(param.chainingSize)(Input(Bool())))
}

/**
* Monitor signals in [[v.StoreUnit]]
* Monitor signals in [[v.SimpleAccessUnit]]
*/
class StoreUnitMonitor extends PerfMonitor {
val vrfReadyToStore = dpiIn("VrfReadyToStore", Input(Bool()))
}
class OtherUnitMonitor extends PerfMonitor {
val lsuRequestIsValid = dpiIn("lsuRequestIsValid", Input(Bool()))

class StoreUnitAlignedDequeueMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor
val s0EnqueueValid = dpiIn("s0EnqueueValid", Input(Bool()))
val stateIsRequest = dpiIn("stateIsRequest", Input(Bool()))
val maskCheck = dpiIn("maskCheck", Input(Bool()))
val indexCheck = dpiIn("indexCheck", Input(Bool()))
val fofCheck = dpiIn("fofCheck", Input(Bool()))

class StoreUnitTlPortAMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
val s0Fire = dpiIn("s0Fire", Input(Bool()))
val s1Fire = dpiIn("s1Fire", Input(Bool()))
val s2Fire = dpiIn("s2Fire", Input(Bool()))

class StoreUnitVrfReadDataPortMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor
val tlPortAIsReady = dpiIn("tlPortAIsReady", Input(Bool()))
val tlPortAIsValid = dpiIn("tlPortAIsValid", Input(Bool()))
val s1Valid = dpiIn("s1Valid", Input(Bool()))
val sourceFree = dpiIn("sourceFree", Input(Bool()))

class LaneReadBusPortMonitor extends IndexedPerfMonitor {
val readBusPortEnqReady = dpiIn("readBusPortEnqReady", Input(Bool()))
val readBusPortEnqValid = dpiIn("readBusPortEnqValid", Input(Bool()))
val readBusPortDeqReady = dpiIn("readBusPortDeqReady", Input(Bool()))
val readBusPortDeqValid = dpiIn("readBusPortDeqValid", Input(Bool()))
}
val tlPortDIsValid = dpiIn("tlPortDIsValid", Input(Bool()))
val tlPortDIsReady = dpiIn("tlPortDIsReady", Input(Bool()))

class LaneWriteBusPortMonitor extends IndexedPerfMonitor {
val writeBusPortEnqReady = dpiIn("writeBusPortEnqReady", Input(Bool()))
val writeBusPortEnqValid = dpiIn("writeBusPortEnqValid", Input(Bool()))
val writeBusPortDeqReady = dpiIn("writeBusPortDeqReady", Input(Bool()))
val writeBusPortDeqValid = dpiIn("writeBusPortDeqValid", Input(Bool()))
}
// Can't use 'VRF' here cuz it will be parsed as 'v_r_f' at DPI side
val vrfWritePortIsReady = dpiIn("VrfWritePortIsReady", Input(Bool()))
val vrfWritePortIsValid = dpiIn("VrfWritePortIsValid", Input(Bool()))

class LaneRequestMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneResponseMonitor extends IndexedPerfMonitor with ValidMonitor {
val laneResponseFeedbackValid = dpiIn("laneResponseFeedbackValid", Input(Bool()))
val stateValue = dpiIn("stateValue", Input(UInt(32.W)))
}
// End of SimpleAccessUnit monitors definition

class LaneVrfReadMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneVrfWriteMonitor extends IndexedPerfMonitor with ValidMonitor with ReadyMonitor

class LaneStatusMonitor extends IndexedPerfMonitor {
val v0UpdateValid = dpiIn("v0UpdateValid", Input(Bool()))
val writeReadyForLsu = dpiIn("writeReadyForLsu", Input(Bool()))
val vrfReadyToStore = dpiIn("vrfReadyToStore", Input(Bool()))
case class LaneParam(slot: Int)
class LaneMonitor(param: LaneParam) extends PerfMonitor {
val index = dpiIn("index", Input(UInt(32.W)))
val laneRequestValid = dpiIn("laneRequestValid", Input(Bool()))
val laneRequestReady = dpiIn("laneRequestReady", Input(Bool()))
val lastSlotOccupied = dpiIn("lastSlotOccupied", Input(Bool()))
val vrfInstructionWriteReportReady = dpiIn("vrfInstructionWriteReportReady", Input(Bool()))
val slotOccupied = dpiIn("slotOccupied", Seq.fill(param.slot)(Input(Bool())))
val instructionFinished = dpiIn("instructionFinished", Input(UInt(32.W)))
}

class LaneWriteQueueMonitor extends IndexedPerfMonitor with ValidMonitor
class LaneSlotMonitor extends PerfMonitor {
val laneIndex = dpiIn("laneIndex", Input(UInt(32.W)))
val slotIndex = dpiIn("slotIndex", Input(UInt(32.W)))

class LaneReadBusDequeueMonitor extends IndexedPerfMonitor with ValidMonitor
val stage0EnqueueReady = dpiIn("stage0EnqueueReady", Input(Bool()))
val stage0EnqueueValid = dpiIn("stage0EnqueueValid", Input(Bool()))

class CrossLaneMonitor extends IndexedPerfMonitor {
val readValid = dpiIn("crossLaneReadValid", Input(Bool()))
val writeValid = dpiIn("crossLaneWriteValid", Input(Bool()))
}

class LaneReadBusDataMonitor extends IndexedPerfMonitor with ValidMonitor

class LaneWriteBusDataMonitor extends IndexedPerfMonitor with ValidMonitor
// End of Lane monitor
val changingMaskSet = dpiIn("changingMaskSet", Input(Bool()))

class VRequestMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor
val slotActive = dpiIn("slotActive", Input(Bool()))
val slotOccupied = dpiIn("slotOccupied", Input(Bool()))
val pipeFinish = dpiIn("pipeFinish", Input(Bool()))

class VResponseMonitor extends PerfMonitor with ValidMonitor
val stage1DequeueReady = dpiIn("stage1DequeueReady", Input(Bool()))
val stage1DequeueValid = dpiIn("stage1DequeueValid", Input(Bool()))

class VRequestRegMonitor extends PerfMonitor with ValidMonitor
val stage1HasDataOccupied = dpiIn("stage1HasDataOccpied", Input(Bool()))
val stage1Finishing = dpiIn("stage1Finishing", Input(Bool()))

class VRequestRegDequeueMonitor extends PerfMonitor with ValidMonitor with ReadyMonitor
val stage1VrfReadReadyRequest = dpiIn("stage1VrfReadReadyRequest", Seq.fill(3)(Input(Bool())))
val stage1VrfReadValidRequest = dpiIn("stage1VrfReadValidRequest", Seq.fill(3)(Input(Bool())))

class VMaskUnitWriteValidMonitor extends PerfMonitor with ValidMonitor
val executionUnitVfuRequestReady = dpiIn("executionUnitVfuRequestReady", Input(Bool()))
val executionUnitVfuRequestValid = dpiIn("executionUnitVfuRequestValid", Input(Bool()))

class VMaskUnitWriteValidIndexedMonitor extends IndexedPerfMonitor with ValidMonitor

class VMaskUnitReadValidMonitor extends PerfMonitor with ValidMonitor

class VMaskUnitReadValidIndexedMonitor extends IndexedPerfMonitor with ValidMonitor

class VWarReadResultValidMonitor extends PerfMonitor with ValidMonitor

class VDataMonitor extends IndexedPerfMonitor with ValidMonitor

class VSelectffoIndexMonitor extends ValidMonitor

class VDataResultMonitor extends ValidMonitor

class VLaneReadyMonitor extends IndexedPerfMonitor with ReadyMonitor

class VExecutionReadyMonitor extends PerfMonitor with ReadyMonitor
val stage3VrfWriteReady = dpiIn("stage3VrfWriteReady", Input(Bool()))
val stage3VrfWriteValid = dpiIn("stage3VrfWriteValid", Input(Bool()))
}

class VInsnRawReadyMonitor extends PerfMonitor with ReadyMonitor
class LaneLastSlotMonitor() extends LaneSlotMonitor {
val slotShiftValid = dpiIn("slotShiftValid", Input(Bool()))
val decodeResultIsCrossReadOrWrite = dpiIn("decodeResultIsCrossReadOrWrite", Input(Bool()))
val decodeResultIsScheduler = dpiIn("decodeResultIsScheduler", Input(Bool()))

class VSlotReadyMonitor extends PerfMonitor with ReadyMonitor
val stage1ReadFinish = dpiIn("stage1ReadFinish", Input(Bool()))

class VSlotStatIdleMonitor extends IndexedPerfMonitor {
val idle = dpiIn("idle", Input(Bool()))
val stage1sSendCrossReadResultLSB = dpiIn("sSendCrossReadResultLSB", Input(Bool()))
val stage1sSendCrossReadResultMSB = dpiIn("sSendCrossReadResultMSB", Input(Bool()))
val stage1wCrossReadLSB = dpiIn("wCrossReadLSB", Input(Bool()))
val stage1wCrossReadMSB = dpiIn("wCrossReadMSB", Input(Bool()))
}

class VVrfWriteMonitor extends IndexedPerfMonitor with ReadyMonitor with ValidMonitor

// End of Lane monitor
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