[difftest] clock width use 32 instead of 64 to get better log size

chipsalliance · Jun 3, 2024 · ffd8e8c · ffd8e8c
1 parent b03f146
commit ffd8e8c
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
@@ -50,7 +50,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
 
   withClockAndReset(clock, reset) {
     // count cycle for peek tl
-    val cycleCounter = RegInit(0.U(32.W))
+    val cycleCounter = RegInit(0.U(64.W))
     cycleCounter := cycleCounter + 1.U
 
     // memory write