[difftest] add offline-difftest

[difftest] fix wrong record of spike mem/vrf changes

fix wrong record of spike mem/vrf changes with wrong default

[difftest] fix wrong se comparsion in peektl event

[difftest] update peek_tl event. wip

[difftest] add 'cycle' to each probe event for simulation debug

[difftest] fix wrong tl_req_ongoing_burst update

[difftest] clock width use 32 instead of 64 to get better log size

[pdifftest] fix to_rtl_queue behaviour mistake

[difftest] use no-console-logging to fix wrong rtl event record bug

[difftest] add [cycle] for check

[difftest] fix wrong lane number in peek vrf

[difftest] fix wrong arch config

[difftest] fix wrong data width in rtl-event parser

[difftest] float rf change should be fake?? wip

[difftest] fix wrong rd assignment

[difftest] refactor to pass cargo clippy

[difftest] use data instead of wrong _data

[difftest] fix wrong reg idx check

[ipemu] fix wrong probe message

[nix] move offline simulator to outer scope

Signed-off-by: Avimitin <[email protected]>

[nix] add devShell for t1-simulator

Signed-off-by: Avimitin <[email protected]>

[script] add support for filter event log from simulation

Signed-off-by: Avimitin <[email protected]>

[nix] add extra emu-result derivation to get event log from ip emulation

Signed-off-by: Avimitin <[email protected]>

[nix] fix unexpected buildInputs pollution

Signed-off-by: Avimitin <[email protected]>

[script] add support for difftest wrapper

Signed-off-by: Avimitin <[email protected]>

[ci] add detail error detection

Signed-off-by: Avimitin <[email protected]>

[script] use file as rtl-event redirect destination

Signed-off-by: Avimitin <[email protected]>

[tests] remove store to MMIO at exit

Signed-off-by: Avimitin <[email protected]>

[ci] update test case cycle data

[difftest] fix rebase bug

.github/cases/blastoise/default.json

@@ -1,7 +1,7 @@
 {
   "mlir.rvv_vp_intrinsic_add": 386,
-  "mlir.rvv_vp_intrinsic_add_scalable": 581,
-  "mlir.hello": 94,
+  "mlir.rvv_vp_intrinsic_add_scalable": 567,
+  "mlir.hello": 91,
   "mlir.stripmining": 26732,
   "asm.mmm": 92609,
   "asm.smoke": 5017,

.github/cases/machamp/default.json

@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 410,
-  "mlir.rvv_vp_intrinsic_add_scalable": 626,
+  "mlir.rvv_vp_intrinsic_add_scalable": 596,
   "mlir.hello": 95,
   "mlir.stripmining": 14447,
   "asm.mmm": 91473,

.github/cases/sandslash/default.json

@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 432,
-  "mlir.rvv_vp_intrinsic_add_scalable": 734,
+  "mlir.rvv_vp_intrinsic_add_scalable": 702,
   "mlir.hello": 105,
   "mlir.stripmining": 15253,
   "asm.mmm": 91490,

difftest/libspike_interfaces/spike_interfaces.cc

@@ -172,10 +172,6 @@ void state_set_pc(spike_state_t* state, uint64_t pc) {
   state->s->pc = pc;
 }
 
-uint32_t state_get_reg_write_size(spike_state_t* state) {
-  return state->s->log_reg_write.size();
-}
-
 uint32_t state_get_reg(spike_state_t* state, uint32_t index, bool is_fp) {
   if (is_fp) {
     auto &fr = state->s->FPR;
@@ -185,6 +181,20 @@ uint32_t state_get_reg(spike_state_t* state, uint32_t index, bool is_fp) {
   return (uint32_t)xr[index];
 }
 
+uint32_t state_get_reg_write_size(spike_state_t* state) {
+  return state->s->log_reg_write.size();
+}
+
+uint32_t state_get_reg_write_index(spike_state_t* state) {
+  int vec_idx = 0;
+  int i = 0;
+  for (auto [idx, data] : state->s->log_reg_write) {
+    vec_idx |= (idx & 0xf) << (i * 4);
+    i++;
+  }
+  return vec_idx;
+}
+
 uint32_t state_get_mem_write_size(spike_state_t* state) {
   return state->s->log_mem_write.size();
 }

difftest/libspike_interfaces/spike_interfaces_c.h

@@ -40,6 +40,7 @@ uint64_t state_handle_pc(spike_state_t* state, uint64_t new_pc);
 void state_set_pc(spike_state_t* state, uint64_t pc);
 uint32_t state_get_reg(spike_state_t* state, uint32_t index, bool is_fp);
 uint32_t state_get_reg_write_size(spike_state_t* state);
+uint32_t state_get_reg_write_index(spike_state_t* state);
 uint32_t state_get_mem_write_size(spike_state_t* state);
 uint32_t state_get_mem_write_addr(spike_state_t* state, uint32_t index);
 uint64_t state_get_mem_write_value(spike_state_t* state, uint32_t index);

difftest/t1-simulator/default.nix

@@ -1,18 +1,26 @@
 { lib
 , libspike
 , rustPlatform
+, rust-analyzer
 , libspike_interfaces
-, rtl
 }:
 
-rustPlatform.buildRustPackage {
-  name = "t1-simulator";
-  src = with lib.fileset; toSource {
-    root = ./.;
-    fileset = fileFilter (file: file.name != "default.nix") ./.;
+let
+  self = rustPlatform.buildRustPackage {
+    name = "t1-simulator";
+    src = with lib.fileset; toSource {
+      root = ./.;
+      fileset = fileFilter (file: file.name != "default.nix") ./.;
+    };
+    passthru.devShell = self.overrideAttrs (old: {
+      nativeBuildInputs = old.nativeBuildInputs ++ [
+        rust-analyzer
+      ];
+    });
+    buildInputs = [ libspike libspike_interfaces ];
+    cargoLock = {
+      lockFile = ./Cargo.lock;
+    };
   };
-  buildInputs = [ libspike libspike_interfaces ];
-  cargoLock = {
-    lockFile = ./Cargo.lock;
-  };
-}
+in
+self

difftest/t1-simulator/readme.md

@@ -0,0 +1,11 @@
+## Build
+
+```bash
+nix build ".#t1-simulator"
+```
+
+## Develop
+
+```bash
+nix develop '.#t1-simulator.devShell'
+```

difftest/t1-simulator/src/difftest.rs

@@ -0,0 +1,203 @@
+mod dut;
+mod spike;
+
+use dut::*;
+pub use spike::SpikeHandle;
+use std::path::Path;
+use tracing::{error, trace};
+
+pub struct Difftest {
+  spike: SpikeHandle,
+  dut: Dut,
+}
+
+impl Difftest {
+  pub fn new(
+    size: usize,
+    elf_file: String,
+    log_file: String,
+    vlen: u32,
+    dlen: u32,
+    set: String,
+  ) -> Self {
+    Self {
+      spike: SpikeHandle::new(size, Path::new(&elf_file), vlen, dlen, set),
+      dut: Dut::new(Path::new(&log_file)),
+    }
+  }
+
+  fn peek_issue(&mut self, issue: IssueEvent) -> anyhow::Result<()> {
+    self.spike.peek_issue(issue).unwrap();
+
+    Ok(())
+  }
+
+  fn update_lsu_idx(&mut self, lsu_enq: LsuEnqEvent) -> anyhow::Result<()> {
+    self.spike.update_lsu_idx(lsu_enq).unwrap();
+
+    Ok(())
+  }
+
+  fn poke_inst(&mut self) -> anyhow::Result<()> {
+    loop {
+      let se = self.spike.find_se_to_issue();
+      if (se.is_vfence_insn || se.is_exit_insn) && self.spike.to_rtl_queue.len() == 1 {
+        if se.is_exit_insn {
+          error!("Simulation quit graceful");
+          return Err(anyhow::anyhow!("graceful exit"));
+        }
+
+        self.spike.to_rtl_queue.pop_back();
+      } else {
+        break;
+      }
+    }
+
+    // TODO: remove these, now just for aligning online difftest
+    if let Some(se) = self.spike.to_rtl_queue.front() {
+      // it is ensured there are some other instruction not committed, thus
+      // se_to_issue should not be issued
+      if se.is_vfence_insn || se.is_exit_insn {
+        assert!(
+          self.spike.to_rtl_queue.len() > 1,
+          "to_rtl_queue are smaller than expected"
+        );
+        if se.is_exit_insn {
+          trace!("DPIPokeInst: exit waiting for fence");
+        } else {
+          trace!("DPIPokeInst: waiting for fence, no issuing new instruction");
+        }
+      } else {
+        trace!(
+          "DPIPokeInst: poke instruction: pc={:#x}, inst={}",
+          se.pc,
+          se.disasm
+        );
+      }
+    }
+    Ok(())
+  }
+
+  pub fn diff(&mut self) -> anyhow::Result<()> {
+    self.poke_inst().unwrap();
+
+    let event = self.dut.step()?;
+
+    match &*event.event {
+      "peekTL" => {
+        let idx = event.parameter.idx.unwrap();
+        // assert!(idx < self.spike.config.dlen / 32);
+        let opcode = event.parameter.opcode.unwrap();
+        let param = event.parameter.param.unwrap();
+        let source = event.parameter.source.unwrap();
+        let mask = event.parameter.mask.unwrap();
+        let data = event.parameter.data.unwrap();
+        let corrupt = event.parameter.corrupt.unwrap();
+        let dready = event.parameter.dready.unwrap() != 0;
+        let cycle = event.parameter.cycle.unwrap();
+        // check align
+        let addr = event.parameter.address.unwrap();
+        let size = (1 << event.parameter.size.unwrap()) as usize;
+        assert_eq!(
+          addr as usize % size,
+          0,
+          "[{cycle}] unaligned access (addr={addr:08X}, size={size}"
+        );
+
+        let opcode = Opcode::from_u32(opcode);
+        self
+          .spike
+          .peek_tl(&PeekTLEvent {
+            idx,
+            opcode,
+            param,
+            size,
+            source,
+            addr,
+            mask,
+            data,
+            corrupt,
+            dready,
+            cycle,
+          })
+          .unwrap();
+      }
+      "issue" => {
+        let idx = event.parameter.idx.unwrap();
+        let cycle = event.parameter.cycle.unwrap();
+        self.peek_issue(IssueEvent { idx, cycle }).unwrap();
+      }
+      "lsuEnq" => {
+        let enq = event.parameter.enq.unwrap();
+        let cycle = event.parameter.cycle.unwrap();
+        self.update_lsu_idx(LsuEnqEvent { enq, cycle }).unwrap();
+      }
+      "vrfWriteFromLsu" => {
+        let idx = event.parameter.idx.unwrap();
+        let vd = event.parameter.vd.unwrap();
+        let offset = event.parameter.offset.unwrap();
+        let mask = event.parameter.mask.unwrap();
+        let data = event.parameter.data.unwrap();
+        let instruction = event.parameter.instruction.unwrap();
+        let lane = event.parameter.lane.unwrap();
+        let cycle = event.parameter.cycle.unwrap();
+        assert!(idx < self.spike.config.dlen / 32);
+
+        self
+          .spike
+          .peek_vrf_write_from_lsu(VrfWriteEvent {
+            idx: lane.trailing_zeros(),
+            vd,
+            offset,
+            mask,
+            data,
+            instruction,
+            cycle,
+          })
+          .unwrap();
+      }
+      "vrfWriteFromLane" => {
+        let idx = event.parameter.idx.unwrap();
+        let vd = event.parameter.vd.unwrap();
+        let offset = event.parameter.offset.unwrap();
+        let mask = event.parameter.mask.unwrap();
+        let data = event.parameter.data.unwrap();
+        let instruction = event.parameter.instruction.unwrap();
+        let cycle = event.parameter.cycle.unwrap();
+        assert!(idx < self.spike.config.dlen / 32);
+        self
+          .spike
+          .peek_vrf_write_from_lane(VrfWriteEvent {
+            idx,
+            vd,
+            offset,
+            mask,
+            data,
+            instruction,
+            cycle,
+          })
+          .unwrap();
+      }
+      "inst" => {
+        let data = event.parameter.data.unwrap() as u32;
+        let cycle = event.parameter.cycle.unwrap();
+        // let vxsat = event.parameter.vxsat.unwrap();
+        // let rd_valid = event.parameter.rd_valid.unwrap();
+        // let rd = event.parameter.rd.unwrap();
+        // let mem = event.parameter.mem.unwrap();
+
+        let se = self.spike.to_rtl_queue.back().unwrap();
+        se.record_rd_write(data).unwrap();
+        se.check_is_ready_for_commit(cycle).unwrap();
+
+        self.spike.to_rtl_queue.pop_back();
+      }
+      "skip" => {}
+      _ => {
+        panic!("unknown event: {}", event.event)
+      }
+    }
+
+    Ok(())
+  }
+}