[difftest] use no-console-logging to fix wrong rtl event record bug

difftest/t1-simulator/src/difftest/spike.rs

@@ -430,21 +430,18 @@ impl SpikeHandle {
 
   pub fn update_lsu_idx(&mut self, lsu_enq: LsuEnqEvent) -> anyhow::Result<()> {
     let enq = lsu_enq.enq;
+    assert!(enq > 0, "enq should be greater than 0");
     let cycle = lsu_enq.cycle;
-    let lsu_reqs: Vec<u32> = (0..MSHR).map(|i| ((enq >> i) & 1) as u32).collect();
 
     if let Some(se) = self
       .to_rtl_queue
       .iter_mut()
       .rev()
-      .find(|se| se.is_issued && (se.is_load || se.is_store) && (se.lsu_idx == LSU_IDX_DEFAULT))
+      .find(|se| se.is_issued && (se.is_load || se.is_store) && se.lsu_idx == LSU_IDX_DEFAULT)
     {
-      if let Some(index) = lsu_reqs.iter().position(|&req| req == 1) {
-        se.lsu_idx = index as u8;
-        info!("[{cycle}] UpdateLSUIdx: Instruction is allocated with pc: {:#x}, inst: {} and lsu_idx: {index}", se.pc, se.disasm);
-      } else {
-        info!("[{cycle}] UpdateLSUIdx: waiting for lsu request to fire");
-      }
+      let index = enq.trailing_zeros() as u8;
+      se.lsu_idx = index;
+      info!("[{cycle}] UpdateLSUIdx: Instruction is allocated with pc: {:#x}, inst: {} and lsu_idx: {index}", se.pc, se.disasm);
     }
     Ok(())
   }
@@ -468,10 +465,10 @@ impl SpikeHandle {
       return Ok(());
     }
 
-    Err(anyhow::anyhow!(
-      "cannot find se with issue_idx={}",
+    panic!(
+      "[{cycle}] cannot find se with issue_idx={}",
       vrf_write.instruction
-    ))
+    )
   }
 
   pub fn peek_vrf_write_from_lane(&mut self, vrf_write: VrfWriteEvent) -> anyhow::Result<()> {
@@ -580,7 +577,6 @@ impl SpikeHandle {
             .fold(String::new(), |acc, x| acc + &format!("{:02X} ", x));
           info!("[{cycle}] SpikeReceiveTLReq: <- receive rtl mem get req: channel={idx}, base_addr={base_addr:08X}, size={size}, mask={mask:b}, source={source}, return_data={hex_actual_data}");
 
-          trace!("get tl_req_record_of_bank[{idx}] insert [{cycle}]");
           self.tl_req_record_of_bank[idx].insert(
             cycle,
             TLReqRecord::new(
@@ -636,7 +632,6 @@ impl SpikeHandle {
               Opcode::PutFullData,
               1,
             );
-            trace!("put full is none: get tl_req_record_of_bank[{idx}] insert [{cycle}]");
             self.tl_req_record_of_bank[idx].insert(cycle, record);
 
             // record moved into self.tl_req_record_of_bank, so we should get it from there
@@ -701,6 +696,6 @@ impl SpikeHandle {
       return Ok(());
     }
 
-    Err(anyhow::anyhow!("cannot find se with issue_idx={lsu_idx}"))
+    panic!("[{cycle}] cannot find se with lsu_idx={lsu_idx}")
   }
 }

tests/builder.nix

@@ -74,6 +74,7 @@ let
         --emulator-path ${ip-emu}/bin/emulator \
         --config ${elaborateConfigJson} \
         --case ${caseDrv}/bin/${pname}.elf \
+        --no-console-logging \
         --out-dir $out
     '';
   } // overrides);