[rtl] Processing cross write tokens.

chipsalliance · May 29, 2024 · f12cbee · f12cbee
1 parent 82fa57c
commit f12cbee
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Showing 4 changed files with 12 additions and 11 deletions.
diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
@@ -248,8 +248,8 @@ class InstructionControlRecord(param: LaneParameter) extends Bundle {
   /** this is the last lane for mask type instruction */
   val isLastLaneForInstruction: Bool = Bool()
 
-  // Requires an additional set of cross-lane reads
-  val additionalRead: Bool = Bool()
+  // Requires an additional set of cross-lane reads/writes
+  val additionalRW: Bool = Bool()
 
   /** the find first one instruction is finished by other lanes,
     * for example, sbf(set before first)

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -524,11 +524,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
       /** We will ignore the effect of mask since:
         * [[Decoder.crossRead]]: We need to read data to another lane
+        * [[Decoder.crossWrite]]: We need to send cross write report to another lane
         * [[Decoder.scheduler]]: We need to synchronize with [[T1]] every group
         * [[record.laneRequest.loadStore]]: We need to read data to lsu every group
         */
-      val alwaysNextGroup: Bool = decodeResult(Decoder.crossRead) || decodeResult(Decoder.nr) ||
-        !decodeResult(Decoder.scheduler) || record.laneRequest.loadStore
+      val alwaysNextGroup: Bool = decodeResult(Decoder.crossRead) || decodeResult(Decoder.crossWrite) ||
+        decodeResult(Decoder.nr) || !decodeResult(Decoder.scheduler) || record.laneRequest.loadStore
 
       // mask not use for mask element
       val maskNotMaskedElement = !record.laneRequest.mask ||
@@ -592,7 +593,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       laneState.instructionIndex := record.laneRequest.instructionIndex
       laneState.skipEnable := skipEnable
       laneState.ffoByOtherLanes := record.ffoByOtherLanes
-      laneState.additionalRead := record.additionalRead
+      laneState.additionalRW := record.additionalRW
       laneState.skipRead := record.laneRequest.decodeResult(Decoder.other) &&
         (record.laneRequest.decodeResult(Decoder.uop) === 9.U)
 
@@ -1076,8 +1077,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     isEndLane && misalignedForOther
   )
 
-  entranceControl.additionalRead :=
-    laneRequest.bits.decodeResult(Decoder.crossRead) &&
+  entranceControl.additionalRW :=
+    (laneRequest.bits.decodeResult(Decoder.crossRead) || laneRequest.bits.decodeResult(Decoder.crossWrite)) &&
       lanePositionLargerThanEndLane && !lastLaneIndex.andR && csrInterface.vl.orR
 
   // slot needs to be moved, try to shifter and stall pipe

diff --git a/t1/src/laneStage/LaneStage.scala b/t1/src/laneStage/LaneStage.scala
@@ -36,7 +36,7 @@ class LaneState(parameter: LaneParameter) extends Bundle {
   val vd: UInt = UInt(5.W)
 
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
-  val additionalRead: Bool = Bool()
+  val additionalRW: Bool = Bool()
   // skip vrf read in stage 1?
   val skipRead: Bool = Bool()
 }

diff --git a/t1/src/laneStage/LaneStage0.scala b/t1/src/laneStage/LaneStage0.scala
@@ -41,7 +41,7 @@ class LaneStage0Enqueue(parameter: LaneParameter) extends Bundle {
   val vd: UInt = UInt(5.W)
 
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
-  val additionalRead: Bool = Bool()
+  val additionalRW: Bool = Bool()
   // skip vrf read in stage 1?
   val skipRead: Bool = Bool()
   // vm will skip element?
@@ -101,9 +101,9 @@ class LaneStage0(parameter: LaneParameter, isLastSlot: Boolean) extends
   )) || enqueue.bits.maskNotMaskedElement ||
     enqueue.bits.decodeResult(Decoder.maskDestination) || enqueue.bits.decodeResult(Decoder.red) ||
     enqueue.bits.decodeResult(Decoder.readOnly) ||  enqueue.bits.loadStore || enqueue.bits.decodeResult(Decoder.gather) ||
-    enqueue.bits.decodeResult(Decoder.crossRead)
+    enqueue.bits.decodeResult(Decoder.crossRead) || enqueue.bits.decodeResult(Decoder.crossWrite)
   // 超出范围的一组不压到流水里面去
-  val enqFire: Bool = enqueue.fire && (!updateLaneState.outOfExecutionRange || enqueue.bits.additionalRead) && notMaskedAllElement
+  val enqFire: Bool = enqueue.fire && (!updateLaneState.outOfExecutionRange || enqueue.bits.additionalRW) && notMaskedAllElement
   val stageDataReg: Data = RegEnable(stageWire, 0.U.asTypeOf(stageWire), enqFire)
   val filterVec: Seq[(Bool, UInt)] = Seq(0, 1, 2).map { filterSew =>
     // The lower 'dataGroupIndexSize' bits represent the offsets in the data group