[rocketv] change icache axi width blockBytes -> fetchBytes.

chipsalliance · Nov 18, 2024 · e72520d · e72520d
1 parent fb6ecc7
commit e72520d
Showing 1 changed file with 7 additions and 3 deletions.
diff --git a/rocketv/src/ICache.scala b/rocketv/src/ICache.scala
@@ -41,7 +41,7 @@ case class ICacheParameter(
   val hasUncorrekoctable:        Boolean                     = itimBaseAddr.nonEmpty && dataCode.canDetect
   val isDM:                      Boolean                     = nWays == 1
   // axi data with
-  val rowBits:                   Int                         = blockBytes * 8
+  val rowBits:                   Int                         = fetchBytes * 8
   val refillCycles:              Int                         = blockBytes * 8 / rowBits
   val blockOffBits:              Int                         = log2Up(blockBytes)
   val idxBits:                   Int                         = log2Up(nSets)
@@ -542,8 +542,12 @@ class ICache(val parameter: ICacheParameter)
   for ((data_array, i) <- icacheDataSRAM.zipWithIndex) {
 
     /** bank match (vaddr[2]) */
-    def wordMatch(addr: UInt): Bool =
-      addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+    def wordMatch(addr: UInt): Bool = {
+      if (io.instructionFetchAXI.r.bits.data.getWidth == wordBits) { true.B } else {
+        addr(log2Ceil(io.instructionFetchAXI.r.bits.data.getWidth / 8) - 1, log2Ceil(wordBits / 8)) === i.U
+      }
+    }
+
     // TODO: if we have last? do we need refillCycles?
     def row(addr: UInt) = addr(untagBits - 1, blockOffBits - log2Ceil(refillCycles))