[difftest & tests] move EXIT_POS to mmio space (0x40000000 -> 0x10000…

…000)
chipsalliance · Nov 27, 2024 · e643f23 · e643f23
1 parent dc4c637
commit e643f23
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Showing 6 changed files with 9 additions and 10 deletions.
diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs
@@ -194,28 +194,27 @@ impl AddressSpace {
 
 /// Memory map:
 /// - 0x0400_0000 - 0x0600_0000 : framebuffer
-/// - 0x4000_0000 - 0x4000_1000 : simctrl
+/// - 0x1000_0000 - 0x1000_1000 : simctrl
 /// - 0x2000_0000 - 0xc000_0000 : ddr
 /// - 0xc000_0000 - 0xc040_0000 : sram
-/// TODO: simctrl is inside ddr, move it elsewhere
 pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) {
   const DDR_BASE: u32 = 0x2000_0000;
   const DDR_SIZE: u32 = 0xa000_0000;
   const SRAM_BASE: u32 = 0xc000_0000;
   const SRAM_SIZE: u32 = 0x0040_0000;
 
-  const SIMCTRL_BASE: u32 = 0x4000_0000;
+  const SIMCTRL_BASE: u32 = 0x1000_0000;
   const SIMCTRL_SIZE: u32 = 0x0000_1000; // one page
   const DISPLAY_BASE: u32 = 0x0400_0000;
   const DISPLAY_SIZE: u32 = 0x0200_0000;
 
   let exit_flag = ExitFlagRef::new();
 
   let devices = vec![
-    SimCtrl::new(exit_flag.clone()).with_addr(SIMCTRL_BASE, SIMCTRL_SIZE),
     RegularMemory::with_size(DDR_SIZE).with_addr(DDR_BASE, DDR_SIZE),
     RegularMemory::with_size(SRAM_SIZE).with_addr(SRAM_BASE, SRAM_SIZE),
     FrameBuffer::new().with_addr(DISPLAY_BASE, DISPLAY_SIZE),
+    SimCtrl::new(exit_flag.clone()).with_addr(SIMCTRL_BASE, SIMCTRL_SIZE),
   ];
   (AddressSpace { devices }, exit_flag)
 }
diff --git a/difftest/spike_rs/src/spike_event.rs b/difftest/spike_rs/src/spike_event.rs
@@ -460,8 +460,8 @@ impl SpikeEvent {
       });
       trace!("SpikeMemWrite: addr={addr:x}, value={value:x}, size={size}");
 
-      if addr == 0x4000_0000 && value == 0xdead_beef {
-        trace!("SpikeExit: exit by writing 0xdeadbeef to 0x40000000");
+      if addr == 0x1000_0000 && value == 0xdead_beef {
+        trace!("SpikeExit: exit by writing 0xdeadbeef to 0x10000000");
         self.is_exit = true;
 
         return;

diff --git a/tests/codegen/include/riscv_test.h b/tests/codegen/include/riscv_test.h
@@ -157,7 +157,7 @@
 
 // Write our custom CSR msimend to exit simulation.
 #define RVTEST_CODE_END                                                        \
-  li x1, 0x40000000;                                                           \
+  li x1, 0x10000000;                                                           \
   li x2, 0xdeadbeef;                                                           \
   sw x2, 0(x1);                                                                \
   j .;

diff --git a/tests/emurt/emurt.c b/tests/emurt/emurt.c
@@ -54,7 +54,7 @@ int _write(int file, char* ptr, int len) {
 }
 
 void _exit(int code) {
-  __asm__("li x1, 0x40000000");
+  __asm__("li x1, 0x10000000");
   __asm__("li x2, 0xdeadbeef");
   __asm__("sw x2, 0(x1)");
   __asm__("j .");

diff --git a/tests/riscv-test-env/p/riscv_test.h b/tests/riscv-test-env/p/riscv_test.h
@@ -237,7 +237,7 @@ reset_vector:                                                           \
 // End Macro
 //-----------------------------------------------------------------------
 
-#define EXIT_POS 0x40000000;
+#define EXIT_POS 0x10000000;
 #define EXIT_CODE 0xdeadbeef;
 #define RVTEST_CODE_END                                                 \
         li x1, EXIT_POS;                                                \

diff --git a/tests/t1_main.S b/tests/t1_main.S
@@ -10,7 +10,7 @@ _start:
     call test
 
     // exit
-    li x1, 0x40000000
+    li x1, 0x10000000
     li x2, 0xdeadbeef
     sw x2, 0(x1)
     j .