[rtl] Adding write back pressure.

chipsalliance · Nov 11, 2024 · e23fab1 · e23fab1
1 parent 8a02a8c
commit e23fab1
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -619,9 +619,10 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val executeReady:        Bool = Wire(Bool())
   // todo: remove, it will do nothing when vl=0
   val sendInitData:        Bool = unitType(2) && !readVS1Reg.sendToExecution && instReg.vl === 0.U
+  val executeDeqReady:     Bool = VecInit(maskedWrite.in.map(_.ready)).asUInt.andR
   val otherTypeRequestDeq: Bool =
     Mux(noSource, noSourceValid, allDataValid || sendInitData) &&
-      vs1DataValid && instVlValid || mvRd
+      vs1DataValid && instVlValid && executeDeqReady || mvRd
   val requestStageDeq:     Bool = Mux(readType, readTypeRequestDeq, otherTypeRequestDeq && executeReady)
   val readIssueStageEnq:   Bool =
     (allDataValid || slideAddressGen.indexDeq.valid) &&