[rtl] Get readResultValid with pipe read.fire

chipsalliance · Dec 24, 2024 · dd8b4aa · dd8b4aa
1 parent 444d8c8
commit dd8b4aa
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Showing 4 changed files with 20 additions and 9 deletions.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -327,6 +327,7 @@ case class T1Parameter(
     transferSize = lsuTransposeSize,
     vrfReadLatency = vrfReadLatency,
     axi4BundleParameter = axi4BundleParameter,
+    lsuReadShifterSize = lsuReadShifterSize,
     name = "main"
   )
   def vrfParam:   VRFParam       = VRFParam(vLen, laneNumber, datapathWidth, chainingSize, vrfBankSize, vrfRamType)

diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -37,6 +37,7 @@ case class LSUParameter(
   // TODO: refactor to per lane parameter.
   vrfReadLatency:      Int,
   axi4BundleParameter: AXI4BundleParameter,
+  lsuReadShifterSize:  Seq[Int],
   name: String) {
   val sewMin: Int = 8
 
@@ -61,7 +62,7 @@ case class LSUParameter(
   val sourceQueueSize: Int = 32.min(vLen * 8 / (transferSize * 8))
 
   def mshrParam: MSHRParam =
-    MSHRParam(chainingSize, datapathWidth, vLen, laneNumber, paWidth, transferSize, vrfReadLatency)
+    MSHRParam(chainingSize, datapathWidth, vLen, laneNumber, paWidth, transferSize, lsuReadShifterSize, vrfReadLatency)
 
   /** see [[VRFParam.regNumBits]] */
   val regNumBits: Int = log2Ceil(32)
@@ -262,8 +263,10 @@ class LSU(param: LSUParameter) extends Module {
     storeUnit.vrfReadResults(index)         := vrfReadResults(index)
   }
   otherUnit.vrfReadDataPorts.ready := (otherTryReadVrf & VecInit(vrfReadDataPorts.map(_.ready)).asUInt).orR
+  // todo: require all shifter same as head
+  val readLatency:     Int           = param.vrfReadLatency + param.lsuReadShifterSize.head * 2
   val pipeOtherRead:   ValidIO[UInt] =
-    Pipe(otherUnit.vrfReadDataPorts.fire, otherUnit.status.targetLane, param.vrfReadLatency)
+    Pipe(otherUnit.vrfReadDataPorts.fire, otherUnit.status.targetLane, readLatency)
   // todo: read data reorder
   otherUnit.vrfReadResults.bits  := Mux1H(pipeOtherRead.bits, vrfReadResults.map(_.bits))
   otherUnit.vrfReadResults.valid := pipeOtherRead.valid

diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
@@ -44,12 +44,13 @@ import org.chipsalliance.dwbb.stdlib.queue.{Queue, QueueIO}
   *     stride and stride instruction
   */
 case class MSHRParam(
-  chainingSize:     Int,
-  datapathWidth:    Int,
-  vLen:             Int,
-  laneNumber:       Int,
-  paWidth:          Int,
-  lsuTransposeSize: Int,
+  chainingSize:       Int,
+  datapathWidth:      Int,
+  vLen:               Int,
+  laneNumber:         Int,
+  paWidth:            Int,
+  lsuTransposeSize:   Int,
+  lsuReadShifterSize: Seq[Int],
   vrfReadLatency: Int) {
 
   /** see [[LaneParameter.lmulMax]] */

diff --git a/t1/src/lsu/StoreUnit.scala b/t1/src/lsu/StoreUnit.scala
@@ -118,9 +118,15 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
       readPort.bits.offset           := readCount
       readPort.bits.instructionIndex := lsuRequestReg.instructionIndex
 
+      val readResultValid = Pipe(
+        readPort.fire,
+        0.U.asTypeOf(new EmptyBundle),
+        param.vrfReadLatency + 2 * param.lsuReadShifterSize(laneIndex)
+      ).valid
+
       // latency queue enq
       AssertProperty(BoolSequence(!vrfReadQueueVec(laneIndex).enq.valid || vrfReadQueueVec(laneIndex).enq.ready))
-      vrfReadQueueVec(laneIndex).enq.valid := vrfReadResults(laneIndex).valid
+      vrfReadQueueVec(laneIndex).enq.valid := readResultValid
       vrfReadQueueVec(laneIndex).enq.bits  := vrfReadResults(laneIndex).bits
       stageValid || readCounter.orR
     }