[tests] update test env macro

Signed-off-by: Avimitin <[email protected]>
chipsalliance · Dec 25, 2024 · d57c412 · d57c412
1 parent 77c506d
commit d57c412
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Showing 3 changed files with 27 additions and 8 deletions.
diff --git a/tests/codegen/include/riscv_test.h b/tests/codegen/include/riscv_test.h
@@ -16,14 +16,14 @@
   RVTEST_FP_ENABLE;                                                     \
   .endm
 
-#define RVTEST_RV64UV                                                          \
-  .macro init;                                                                 \
-  RVTEST_VECTOR_ENABLE;                                                        \
+#define RVTEST_RV64UV                                                   \
+  .macro init;                                                          \
+  RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
-#define RVTEST_RV64UFV                                                  \
+#define RVTEST_RV64UVX                                                  \
   .macro init;                                                          \
-  RVTEST_FP_VECTOR_ENABLE;                                              \
+  RVTEST_ZVE32X_ENABLE;                                                 \
   .endm
 
 #define RVTEST_RV32U                                                    \
@@ -40,6 +40,11 @@
   RVTEST_VECTOR_ENABLE;                                                        \
   .endm
 
+#define RVTEST_RV32UVX                                                         \
+  .macro init;                                                                 \
+  RVTEST_ZVE32X_ENABLE;                                                        \
+  .endm
+
 #define INIT_XREG                                                              \
   li x1, 0;                                                                    \
   li x2, 0;                                                                    \
@@ -115,14 +120,14 @@
   csrs mstatus, a0;                                                            \
   csrwi fcsr, 0
 
-#define RVTEST_FP_VECTOR_ENABLE                                                \
+#define RVTEST_VECTOR_ENABLE                                                   \
   li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1));  \
   csrs mstatus, a0;                                                            \
   csrwi fcsr, 0;                                                               \
   csrwi vcsr, 0;
 
-#define RVTEST_VECTOR_ENABLE                                                   \
-  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1));  \
+#define RVTEST_ZVE32X_ENABLE                                                   \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1));                                     \
   csrs mstatus, a0;                                                            \
   csrwi vcsr, 0;
 

diff --git a/tests/riscv-test-env/p/riscv_test.h b/tests/riscv-test-env/p/riscv_test.h
@@ -23,6 +23,11 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV64UVX                                                  \
+  .macro init;                                                          \
+  RVTEST_ZVE32X_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV32U                                                    \
   .macro init;                                                          \
   .endm
@@ -37,6 +42,11 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV32UVX                                                  \
+  .macro init;                                                          \
+  RVTEST_ZVE32X_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV64M                                                    \
   .macro init;                                                          \
   RVTEST_ENABLE_MACHINE;                                                \

diff --git a/tests/riscv-test-env/v/riscv_test.h b/tests/riscv-test-env/v/riscv_test.h
@@ -17,6 +17,10 @@
   csrwi fcsr, 0;                                                        \
   csrwi vcsr, 0;
 
+#undef RVTEST_ZVE32X_ENABLE
+#define RVTEST_ZVE32X_ENABLE                                            \
+  csrwi vcsr, 0;
+
 #undef RVTEST_CODE_BEGIN
 #define RVTEST_CODE_BEGIN                                               \
         .text;                                                          \