[rtl] fix T1Interface.

chipsalliance · Jul 25, 2024 · d4a0c21 · d4a0c21
1 parent 03746ae
commit d4a0c21
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -1437,7 +1437,7 @@ class T1(val parameter: T1Parameter)
     decodeResult(Decoder.nr),
     // evl for Whole Vector Register Move ->  vs1 * (vlen / datapathWidth)
     (requestRegDequeue.bits.instruction(17, 15) +& 1.U) ## 0.U(log2Ceil(parameter.vLen / parameter.datapathWidth).W),
-    T1Issue.vsew(requestReg.bits.issue)
+    requestReg.bits.issue.vl
   )
 
   val vSewForLsu: UInt = Mux(lsWholeReg, 2.U, requestRegDequeue.bits.instruction(13, 12))