[rtl] Do not steal data with unread instructions.

chipsalliance · Jun 3, 2024 · ce35852 · ce35852
1 parent cdd392e
commit ce35852
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/laneStage/LaneStage1.scala b/t1/src/laneStage/LaneStage1.scala
@@ -378,7 +378,7 @@ class LaneStage1(parameter: LaneParameter, isLastSlot: Boolean) extends Module {
   val allDataQueueValid: Bool = VecInit(dataQueueValidVec).asUInt.andR
   dequeue.valid := allDataQueueValid && pipeQueue.io.deq.valid
   dataQueueVs1.ready := allDataQueueValid && dequeue.ready && pipeQueue.io.deq.bits.decodeResult(Decoder.vtype)
-  dataQueueVs2.io.deq.ready := allDataQueueValid && dequeue.ready
+  dataQueueVs2.io.deq.ready := allDataQueueValid && dequeue.ready && !pipeQueue.io.deq.bits.skipRead
   dataQueueVd.io.deq.ready :=
     allDataQueueValid && dequeue.ready && !pipeQueue.io.deq.bits.decodeResult(Decoder.sReadVD)
   crossReadResultQueue.foreach(_.io.deq.ready := allDataQueueValid && dequeue.ready && pipeQueue.io.deq.bits.decodeResult(Decoder.crossRead))