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// SPDX-License-Identifier: Apache-2.0 | ||
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]> | ||
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package org.chipsalliance.t1.rtl.decoder.attribute | ||
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import org.chipsalliance.t1.rtl.decoder.T1DecodePattern | ||
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trait AdderUOPType extends Uop | ||
object T0 extends AdderUOPType | ||
object T1 extends AdderUOPType | ||
object T2 extends AdderUOPType | ||
object T3 extends AdderUOPType | ||
object T4 extends AdderUOPType | ||
object T5 extends AdderUOPType | ||
object T6 extends AdderUOPType | ||
object T7 extends AdderUOPType | ||
object T8 extends AdderUOPType | ||
object T9 extends AdderUOPType | ||
object T10 extends AdderUOPType | ||
object T11 extends AdderUOPType | ||
object T12 extends AdderUOPType | ||
object T13 extends AdderUOPType | ||
object T14 extends AdderUOPType | ||
object T15 extends AdderUOPType | ||
object DC extends AdderUOPType | ||
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object AdderUOP { | ||
def apply(t1DecodePattern: T1DecodePattern): AdderUOPType = { | ||
Seq( | ||
t0 _ -> T0, | ||
t1 _ -> T1, | ||
t2 _ -> T2, | ||
t3 _ -> T3, | ||
t4 _ -> T4, | ||
t5 _ -> T5, | ||
t6 _ -> T6, | ||
t7 _ -> T7, | ||
t8 _ -> T8, | ||
t9 _ -> T9, | ||
t10 _ -> T10, | ||
t11 _ -> T11, | ||
t12 _ -> T12, | ||
t13 _ -> T13, | ||
t14 _ -> T14, | ||
t15 _ -> T15, | ||
dc _ -> DC, | ||
).collectFirst { | ||
case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) | ||
}.get | ||
} | ||
def t0(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vaadd.vv", | ||
"vaadd.vx", | ||
"vaaddu.vv", | ||
"vaaddu.vx", | ||
"vadd.vi", | ||
"vadd.vv", | ||
"vadd.vx", | ||
"vredsum.vs", | ||
"vsadd.vi", | ||
"vsadd.vv", | ||
"vsadd.vx", | ||
"vsaddu.vi", | ||
"vsaddu.vv", | ||
"vsaddu.vx", | ||
"vwadd.vv", | ||
"vwadd.vx", | ||
"vwadd.wv", | ||
"vwadd.wx", | ||
"vwaddu.vv", | ||
"vwaddu.vx", | ||
"vwaddu.wv", | ||
"vwaddu.wx", | ||
"vwredsum.vs", | ||
"vwredsumu.vs", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t1(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vasub.vv", | ||
"vasub.vx", | ||
"vasubu.vv", | ||
"vasubu.vx", | ||
"vrsub.vi", | ||
"vrsub.vx", | ||
"vssub.vv", | ||
"vssub.vx", | ||
"vssubu.vv", | ||
"vssubu.vx", | ||
"vsub.vv", | ||
"vsub.vx", | ||
"vwsub.vv", | ||
"vwsub.vx", | ||
"vwsub.wv", | ||
"vwsub.wx", | ||
"vwsubu.vv", | ||
"vwsubu.vx", | ||
"vwsubu.wv", | ||
"vwsubu.wx", | ||
"vadc.vim", | ||
"vadc.vvm", | ||
"vadc.vxm", | ||
"vmadc.vi", | ||
"vmadc.vim", | ||
"vmadc.vv", | ||
"vmadc.vvm", | ||
"vmadc.vx", | ||
"vmadc.vxm", | ||
"vmsbc.vv", | ||
"vmsbc.vvm", | ||
"vmsbc.vx", | ||
"vmsbc.vxm", | ||
"vsbc.vvm", | ||
"vsbc.vxm", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t2(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmslt.vv", | ||
"vmslt.vx", | ||
"vmsltu.vv", | ||
"vmsltu.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t3(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmsle.vi", | ||
"vmsle.vv", | ||
"vmsle.vx", | ||
"vmsleu.vi", | ||
"vmsleu.vv", | ||
"vmsleu.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t4(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmsgt.vi", | ||
"vmsgt.vx", | ||
"vmsgtu.vi", | ||
"vmsgtu.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t5(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t6(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmax.vv", | ||
"vmax.vx", | ||
"vmaxu.vv", | ||
"vmaxu.vx", | ||
"vredmax.vs", | ||
"vredmaxu.vs", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t7(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmin.vv", | ||
"vmin.vx", | ||
"vminu.vv", | ||
"vminu.vx", | ||
"vredmin.vs", | ||
"vredminu.vs", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t8(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmseq.vi", | ||
"vmseq.vv", | ||
"vmseq.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t9(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmsne.vi", | ||
"vmsne.vv", | ||
"vmsne.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t10(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vadc.vim", | ||
"vadc.vvm", | ||
"vadc.vxm", | ||
"vmadc.vi", | ||
"vmadc.vim", | ||
"vmadc.vv", | ||
"vmadc.vvm", | ||
"vmadc.vx", | ||
"vmadc.vxm", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t11(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vmsbc.vv", | ||
"vmsbc.vvm", | ||
"vmsbc.vx", | ||
"vmsbc.vxm", | ||
"vsbc.vvm", | ||
"vsbc.vxm", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t12(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t13(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t14(t1DecodePattern: T1DecodePattern): Boolean = | ||
def t15(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def dc(t1DecodePattern: T1DecodePattern): Boolean = false | ||
} | ||
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case class AdderUOP(value: AdderUOPType) extends UopDecodeAttribute[AdderUOPType] { | ||
override val description: String = "" | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,105 @@ | ||
// SPDX-License-Identifier: Apache-2.0 | ||
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]> | ||
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package org.chipsalliance.t1.rtl.decoder.attribute | ||
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import org.chipsalliance.t1.rtl.decoder.T1DecodePattern | ||
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trait DivUOPType extends Uop | ||
object T0 extends DivUOPType | ||
object T1 extends DivUOPType | ||
object T2 extends DivUOPType | ||
object T3 extends DivUOPType | ||
object T4 extends DivUOPType | ||
object T5 extends DivUOPType | ||
object T6 extends DivUOPType | ||
object T7 extends DivUOPType | ||
object T8 extends DivUOPType | ||
object T9 extends DivUOPType | ||
object T10 extends DivUOPType | ||
object T11 extends DivUOPType | ||
object T12 extends DivUOPType | ||
object T13 extends DivUOPType | ||
object T14 extends DivUOPType | ||
object T15 extends DivUOPType | ||
object DC extends DivUOPType | ||
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object DivUOP { | ||
def apply(t1DecodePattern: T1DecodePattern): DivUOPType = { | ||
Seq( | ||
t0 _ -> T0, | ||
t1 _ -> T1, | ||
t2 _ -> T2, | ||
t3 _ -> T3, | ||
t4 _ -> T4, | ||
t5 _ -> T5, | ||
t6 _ -> T6, | ||
t7 _ -> T7, | ||
t8 _ -> T8, | ||
t9 _ -> T9, | ||
t10 _ -> T10, | ||
t11 _ -> T11, | ||
t12 _ -> T12, | ||
t13 _ -> T13, | ||
t14 _ -> T14, | ||
t15 _ -> T15, | ||
dc _ -> DC, | ||
).collectFirst { | ||
case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) | ||
}.get | ||
} | ||
def t0(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vdiv.vv", | ||
"vdiv.vx", | ||
"vdivu.vv", | ||
"vdivu.vx", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t1(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vrem.vv", | ||
"vrem.vx", | ||
"vremu.vv", | ||
"vremu.vx", | ||
"vfrdiv.vf", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t2(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t3(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t4(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t5(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t6(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t7(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t8(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vfdiv.vf", | ||
"vfdiv.vv", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t9(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vfsqrt.v", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t10(t1DecodePattern: T1DecodePattern): Boolean = { | ||
val allMatched: Seq[String] = Seq( | ||
"vfrdiv.vf", | ||
) | ||
allMatched.contains(t1DecodePattern.instruction.name) | ||
} | ||
def t11(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t12(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t13(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t14(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def t15(t1DecodePattern: T1DecodePattern): Boolean = false | ||
def dc(t1DecodePattern: T1DecodePattern): Boolean = false | ||
} | ||
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case class DivUOP(value: DivUOPType) extends UopDecodeAttribute[DivUOPType] { | ||
override val description: String = "" | ||
} |
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